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never stop thinking. microcontrollers data sheet, v1.2, may 2002 tc1775 32-bit single-chip microcontroller
edition 2002-05 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2002. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
microcontrollers data sheet, v1.2, may 2002 never stop thinking. tc1775 32-bit single-chip microcontroller
tc1775 data sheet preliminary revision history: 2002-05 v1.2 previous versions: v1.1, 2001-08; v1.0, 2001-08; page subjects (major changes since last revision) changes from v1.1, 2001-08 to v1.2, 2002-05 ? status of data sheet changed from ?advance information? into ?preliminary? 36 adc features: example of 10-bit adc conversion time added 54 note below figure 16 added 59 column ?jitter? in table 8 removed; the jitter is now defined in ?pll parameters? on page 82 and figure 31 ; 2 nd footnote for table 8 added 60 note on bottom extended ?? specified by the crystal suppliers:? 66 section ?package parameters? added 68 , 69 , 70 definition and values for pull-up/pull-down currents changed 71 curves for pull-up/pull-down characteristics added 73 formulas for conversion time t c corrected; f ana min./max. specification added 73 definition of i aov and k a improved 76 note 1) for i oz added 77 i dd max corrected; i dd active for v ddsb added; note for i id and i sl added 78 t rfanom (typ.) added 80 figure 29 corrected 81 figure 30 corrected 82 , 83 pll specification and parameters completed 84 , 87 , 89 , 92 , 94 , 95 several ac timing parameter values added or corrected: t 10 , t 11 , t 15 , t 20 , t 21 , t 25 , t 45 , t 46 , t 47 , t 55 , t 61 , t 62 95 definition of t 61 and t 62 changed several formal changes changes from v1.0, 2001-08 to v1.1, 2001-08 84 reference for t 31 and t 32 to page 90 added 89 t 50 and t 51 changed into tbd; note changed into ?will be guaranteed ?? 90 t 31 and t 32 (data setup/hold to clkin in burst mode timing) changed; note 1) added 95 t 61 and t 62 changed into tbd; note changed into ?will be guaranteed ?? we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
data sheet 1 v1.2, 2002-05 preliminary tc1775 32-bit single-chip microcontroller tricore family high performance 32-bit tricore cpu with 4-stage pipeline ? 25 ns instruction cycle time at 40 mhz cpu clock dual issue super-scalar implementation ? instruction triple issue circular buffer and bit-reverse addressing modes for dsp algorithms flexible multi-master interrupt system very fast interrupt response time hardware controlled context switch for task switch and interrupts 72 kbytes of on-chip sram for data and time critical code independent peripheral control processor (pcp) for low level driver support with 20 kbytes code/parameter memory built-in calibration support on-chip flexible peripheral interface bus (fpi bus) for interconnections of functional units flexible external bus interface unit (ebu) used for ? communication with external data memories and peripheral units ? instruction fetches from external burst flash program memories on-chip peripheral units ? general purpose timer array (gpta) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex i/o management ? multifunctional general purpose timer unit (gptu) with three 32-bit timer/counters ? two asynchronous/synchronous serial channels (asc0, asc1) with baud rate generator, parity, framing and overrun error detection ? two high speed synchronous serial channels (ssc0, ssc1) with programmable data length and shift direction ? twincan module with two interconnected can nodes for high efficiency data handling via fifo buffering and gateway data transfer ? serial data link module (sdlm) compliant to sae class b j1850 specification ? two analog-to-digital converter units (adc0, adc1) with 8-bit, 10-bit, or 12-bit resolution and 16 analog inputs each ? watchdog timer and system timer ? real time clock eleven 16-bit digital i/o ports and two 16-bit analog ports on-chip debug support power management system clock generation unit with pll ambient temperature under bias: -40 c to +125 c p-bga-329 package
tc1775 data sheet 2 v1.2, 2002-05 preliminary ordering information the ordering code for infineon microcontrollers provides an exact reference to the required product. this ordering code identifies: the derivative itself, i.e. its function set, the temperature range, and the package and the type of delivery. the tc1775 is available with the following ordering code: type ordering code package description sak-tc1775-l40e q67121-c2285-a701 p-bga-329 32-bit single-chip microcontroller 40 mhz -40 c to +125 c
tc1775 data sheet 3 v1.2, 2002-05 preliminary block diagram figure 1 tc1775 block diagram mcb04671 j1850 twin can ssc0 ssc1 asc0 asc1 adc0 adc1 gpta 4 3 3 2 16 ebu (external bus unit) port 4 12 16 port 0 16 16 port 1 16 16 port 2 16 16 addr. [15:0] addr./ data [15:0] addr./ data (31:16] port 13 port 10 16 16 port 9 16 port 8 port 7 port 6 16 16 2 gptu 8 port 11 16 16 port 12 16 5 2 5 2 pcp core ocds interrupt 4 k data-sram fpi interface 2 stm bcu rtc pll fpi bus clkout clkin xtal4 xtal3 f rtc = 32 khz xtal2 xtal1 control f cpumax = 40 mhz port 5 16 16 16 cerberus & jtag scu (p w r ) power- watchdog- reset 5 jta g io brkout brkin control 9 dmu (data memory unit) 32 kb sram + 8 kb stand-by sram (overlay functionality) tricore cpu trace & ocds interrupt v ss v dd 128 64 ocdse pmu (program memory unit) 8 kb boot rom 32 kb scratch pad ram 1 kb instruction cache fpi bus 32 32 16 16 16 16 16 16 ebu control 10 address [25:16] 6 port 3 4 16 k code-sram
tc1775 data sheet 4 v1.2, 2002-05 preliminary logic symbol figure 2 tc1775 logic symbol mca04679 tc 1775 port 0 16-bit port 1 16-bit port 2 16-bit port 3 16-bit port 4 16-bit port 5 16-bit port 6 16-bit port 7 16-bit port 8 16-bit port 9 16-bit port 10 16-bit port 11 16-bit port 12 16-bit port 13 16-bit v aref0 v agnd0 v dda0 v ssa0 v aref1 v agnd1 v dda1 v ssa1 alternate functions external bus interface trace adc0 adc1 gpta adc0/1 j1850 / asc0/1 gptu / ssc0/1 / can adc0 analog power supply adc1 analog power supply v ssm v ddm v sssc v ddsc adc0 / adc1 analog power supply v ss v ddsb v ddsram v ddp813 v ddp05 v dd 10 5 6 2 29 digital circuitry power supply brkout brkin ocdse tms tdo tdi tck trst jtag / ocds v sspll v ddpll v ssosc v ddosc xtal4 xtal3 xtal2 xtal1 oscillators / pll 3 clksel bypass cfg nmi porst hdrst clkout clkin testmode 4 general control 3 n.c.1 7 n.c.2
tc1775 data sheet 5 v1.2, 2002-05 preliminary pin configuration figure 3 tc1775 pinning: p-bga-329 package (top view) mcp04680 an 3 an 6 an 9 1234567 an 11 an 15 89 p12. 13 10 11 p12. 9 p12. 5 12 13 p12. 1 p13 15 14 15 p13. 11 p13. 8 16 17 p13. 4 p13. 2 18 19 p11. 15 p11. 12 20 21 p11. 8 p11. 5 22 23 p11. 4 v ssa0 v ssm v sssc v ddsc a an 16 b an 17 an 0 an 4 an 7 an 10 an 13 p12. 15 p12. 12 p12. 7 p12. 6 p12. 2 p13. 13 p13. 9 p13. 6 p13. 3 p13. 0 p11. 13 p11. 9 p11. 6 p11. 3 v ddsb an 19 c v ddm an 20 an 1 an 5 an 8 an 14 p12. 14 p12. 11 p12. 8 p12. 4 p12. 3 n.c. 2 p13. 14 p13. 10 p13. 7 p13. 1 p11. 14 p11. 10 p11. 0 p11. 1 a b c an 23 d an 24 an 18 an 2 an 21 v ss an 12 v dd p813 v dda0 n.c. 1 p12. 10 p12. 0 p13. 12 v dd v dd p813 p13. 5 v ss p11. 11 p11. 7 n.c. 2 p10. 13 p10. 14 d an 26 e an 27 an 22 an 25 an 29 f an 30 an 28 v ss v aref0 v agnd0 v agnd1 v ssa1 v aref1 an 31 g v dda1 h p1.0 p1.1 v dd p05 p1.2 j p1.4 p1.5 p1.3 p1.6 k p1.7 n.c. 2 v dd p1.8 l p1.9 p1.10 n.c. 2 p1.12 m p1.13 p1.11 v dd p05 p0.0 n p1.14 p1.15 p0.1 p0.4 p p0.3 p0.2 v dd p0.6 p0.5 p0.7 clk out r p0.9 p0.8 clk in t v dd p05 p0.13 u p0.11 p0.10 p0.12 v dd p0.15 v p0.14 p4.0 p4.2 w p4.1 p4.3 p4.6 p4.5 y p4.4 p4.7 p4.15 p2.2 v ss p2.12 v dd p05 p3.3 v dd p3.9 v dd p05 p5.3 n.c. 1 p5.8 n.c. 2 p5.15 v dd ocd se nmi po rst cfg 1 trst cfg 0 f g h j k l m n p r t u v w y e p10. 15 p10. 12 p10. 10 p10. 11 v dd p10. 9 p10. 7 p10. 8 p10. 3 p10. 4 p10. 6 p10. 5 p10. 0 p10. 1 p10. 2 v dd p813 p9.14 p9.12 p9.13 p9.15 v dd p9.9 p9.10 p9.11 p9.6 p9.5 p9.7 p9.8 v dd p813 p9.2 p9.4 p9.3 p9.1 p9.0 p8.15 p8.14 v dd p8.13 p8.12 p8.11 p8.10 p8.9 p8.7 p8.8 v dd p813 p8.6 p8.5 p8.4 p8.3 p8.2 p8.0 p8.1 v ss clk sel0 clk sel2 clk sel1 cfg 2 by pass cfg 3 hd rst aa p4.9 p4.8 p4.10 p2.1 p2.5 p2.8 p2.14 p3.1 p3.5 p3.8 p3.12 p3.13 p5.1 p5.4 p5.7 p5.10 p5.13 tdo xtal 4 v ss osc v dd pll v ss pll aa ab p4.14 p4.11 p2.0 p2.4 p2.7 p2.10 p2.13 p3.0 p3.4 p3.7 p3.11 p3.15 p5.0 p5.5 p5.11 p5.14 n.c. 1 v dd sram tck tms xtal 3 n.c. 2 test mode ab p4.12 p4.13 ac n.c. 2 p2.3 p2.6 p2.9 p2.11 p2.15 p3.2 p3.6 p3.10 p3.14 p5.2 p5.6 p5.9 p5.12 v dd sram brk out tdi brk in v dd osc xtal 2 xtal 1 ac 1 2 3 4 5 6 7 8 9 1011121314151617181920212223 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v dd p11. 2 v dd p813
tc1775 data sheet 6 v1.2, 2002-05 preliminary table 1 pin definitions and functions symbol pin in out functions p0 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.11 p0.12 p0.13 p0.14 p0.15 n1 n4 p3 p2 p1 r3 r2 r4 t3 t2 u3 u2 u4 u1 v2 v1 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 0 port 0 serves as 16-bit general purpose i/o port or as lower external address/data bus ad[15:0] (multiplexed bus mode) or data bus d[15:0] (demultiplexed bus mode) for the ebu. port 0 is used as data input by an external bus master when accessing modules on the internal fpi bus. ad0 / d0 address/data bus line 0 / data bus line 0 ad1 / d1 address/data bus line 1 / data bus line 1 ad2 / d2 address/data bus line 2 / data bus line 2 ad3 / d3 address/data bus line 3 / data bus line 3 ad4 / d4 address/data bus line 4 / data bus line 4 ad5 / d5 address/data bus line 5 / data bus line 5 ad6 / d6 address/data bus line 6 / data bus line 6 ad7 / d7 address/data bus line 7 / data bus line 7 ad8 / d8 address/data bus line 8 / data bus line 8 ad9 / d9 address/data bus line 9 / data bus line 9 ad10 / d10 address/data bus line 10 / data bus line 10 ad11 / d11 address/data bus line 11 / data bus line 11 ad12 / d12 address/data bus line 12 / data bus line 12 ad13 / d13 address/data bus line 13 / data bus line 13 ad14 / d14 address/data bus line 14 / data bus line 14 ad15 / d15 address/data bus line 15 / data bus line 15
tc1775 data sheet 7 v1.2, 2002-05 preliminary p1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p1.8 p1.9 p1.10 p1.11 p1.12 p1.13 p1.14 p1.15 h2 h3 j1 j4 j2 j3 k1 k2 l1 l2 l3 m3 m1 m2 n2 n3 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 1 port 1 serves as 16-bit general purpose i/o port or as upper external address/data bus ad[31:16] (multiplexed bus mode) or data bus d[31:16] (demultiplexed bus mode) for the ebu. port 1 is used as data input by an external bus master when accessing modules on the internal fpi bus. ad16 / d16 address/data bus line 16 / data bus line 16 ad17 / d17 address/data bus line 17/ data bus line 17 ad18 / d18 address/data bus line 18 / data bus line 18 ad19 / d19 address/data bus line 19 / data bus line 19 ad20 / d20 address/data bus line 20 / data bus line 20 ad21 / d21 address/data bus line 21 / data bus line 21 ad22 / d22 address/data bus line 22 / data bus line 22 ad23 / d23 address/data bus line 23 / data bus line 23 ad24 / d24 address/data bus line 24 / data bus line 24 ad25 / d25 address/data bus line 25 / data bus line 25 ad26 / d26 address/data bus line 26 / data bus line 26 ad27 / d27 address/data bus line 27 / data bus line 27 ad28 / d28 address/data bus line 28 / data bus line 28 ad29 / d29 address/data bus line 29 / data bus line 29 ad30 / d30 address/data bus line 30 / data bus line 30 ad31 / d31 address/data bus line 31 / data bus line 31 table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 8 v1.2, 2002-05 preliminary p2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p2.8 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 ab3 aa4 y5 ac4 ab4 aa5 ac5 ab5 aa6 ac6 ab6 ac7 y7 ab7 aa7 ac8 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 2 port 2 serves as 16-bit general purpose i/o port or as lower external address bus for the ebu. when used as address bus, it outputs the addresses a[15:0] of an external access in demultiplexed bus mode. port 2 is used as address input by an external bus master when accessing modules on the internal fpi bus. a0 address bus line 0 a1 address bus line 1 a2 address bus line 2 a3 address bus line 3 a4 address bus line 4 a5 address bus line 5 a6 address bus line 6 a7 address bus line 7 a8 address bus line 8 a9 address bus line 9 a10 address bus line 10 a11 address bus line 11 a12 address bus line 12 a13 address bus line 13 a14 address bus line 14 a15 address bus line 15 table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 9 v1.2, 2002-05 preliminary p3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 1) p3.11 1) p3.12 1) p3.13 1) p3.14 1) p3.15 1) ab8 aa8 ac9 y9 ab9 aa9 ac10 ab10 aa10 y11 ac11 ab11 aa11 aa12 ac12 ab12 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o o o o o o o port 3 port 3 serves as 16-bit general purpose i/o port or as upper external address bus for the ebu. when used as address bus, it outputs the addresses a[25:16] of an external access in demultiplexed bus mode. p3[9:0] is used as address input by an external bus master when accessing modules on the internal fpi bus. port 3 also provides chip select output lines cs0 - cs3 , csemu , and csovl . a16 address bus line 16 a17 address bus line 17 a18 address bus line 18 a19 address bus line 19 a20 address bus line 20 a21 address bus line 21 a22 address bus line 22 a23 address bus line 23 a24 address bus line 24 a25 address bus line 25 cs3 chip select output line 3 cs2 chip select output line 2 cs1 chip select output line 1 cs0 chip select output line 0 csemu chip select output for emulator region csovl chip select output for emulator overlay memory table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 10 v1.2, 2002-05 preliminary p4 p4.0 1) p4.1 1) p4.2 2) p4.3 1) p4.4 1) p4.5 1) p4.6 1) p4.7 1) p4.8 1) p4.9 1) p4.10 1) p4.11 1) p4.12 1) p4.13 1) p4.14 1) p4.15 1) v3 w2 w1 w3 y2 y1 w4 y3 aa2 aa1 aa3 ab1 ac1 ac2 ab2 y4 i/o i/o i/o o o i/o i/o i/o i/o i o i i i/o o o i/o port 4 port 4 is used as general purpose i/o port but also serves as control bus for the ebu control lines. rd read control line rd/wr write control line ale address latch enable output adv address valid output bc0 byte control line 0 bc1 byte control line 1 bc2 byte control line 2 bc3 byte control line 3 wait /ind wait input / end of burst input baa burst address advance output csfpi chip select fpi input hold hold request input hlda hold acknowledge input/output breq bus request output code code fetch status output svm supervisor mode input/output the code signal has the same timing as the csx signals which are located at port 3. table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 11 v1.2, 2002-05 preliminary p5 p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 p5.8 p5.9 p5.10 p5.11 p5.12 p5.13 p5.14 p5.15 ab13 aa13 ac13 y13 aa14 ab14 ac14 aa15 y15 ac15 aa16 ab16 ac16 aa17 ab17 y17 i/o o o o o o o o o o o o o o o o o port 5 port 5 serves as 16-bit general purpose i/o port or as cpu or pcp trace output port for the ocds logic. trace0 cpu or pcp trace output 0 trace1 cpu or pcp trace output 1 trace2 cpu or pcp trace output 2 trace3 cpu or pcp trace output 3 trace4 cpu or pcp trace output 4 trace5 cpu or pcp trace output 5 trace6 cpu or pcp trace output 6 trace7 cpu or pcp trace output 7 trace8 cpu or pcp trace output 8 trace9 cpu or pcp trace output 9 trace10 cpu or pcp trace output 10 trace11 cpu or pcp trace output 11 trace12 cpu or pcp trace output 12 trace13 cpu or pcp trace output 13 trace14 cpu or pcp trace output 14 trace15 cpu or pcp trace output 15 table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 12 v1.2, 2002-05 preliminary p6 p6.0 p6.1 p6.2 p6.3 p6.4 p6.5 p6.6 p6.7 p6.8 p6.9 p6.10 p6.11 p6.12 p6.13 p6.14 p6.15 b3 c4 d5 a4 b4 c5 a5 b5 c6 a6 b6 a7 d7 b7 c7 a8 i i i i i i i i i i i i i i i i i port 6 port 6 provides the analog input lines for the ad converter 0 (adc0). an0 analog input 0 / v aref [1] input for adc0 an1 analog input 1 / v aref [2] input for adc0 an2 analog input 2 / v aref [3] input for adc0 an3 analog input 3 an4 analog input 4 an5 analog input 5 an6 analog input 6 an7 analog input 7 an8 analog input 8 an9 analog input 9 an10 analog input 10 an11 analog input 11 an12 analog input 12 an13 analog input 13 an14 analog input 14 an15 analog input 15 p7 p7.0 p7.1 p7.2 p7.3 p7.4 p7.5 p7.6 p7.7 p7.8 p7.9 p7.10 p7.11 p7.12 p7.13 p7.14 p7.15 b1 b2 d4 c1 c2 d3 e4 d1 d2 e3 e1 e2 f3 f1 f2 g1 i i i i i i i i i i i i i i i i i port 7 port 7 provides the analog input lines for the ad converter 1 (adc1). an16 analog input 16 / v aref [1] input for adc1 an17 analog input 17 / v aref [2] input for adc1 an18 analog input 18 / v aref [3] input for adc1 an19 analog input 19 an20 analog input 20 an21 analog input 21 an22 analog input 22 an23 analog input 23 an24 analog input 24 an25 analog input 25 an26 analog input 26 an27 analog input 27 an28 analog input 28 an29 analog input 29 an30 analog input 30 an31 analog input 31 table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 13 v1.2, 2002-05 preliminary p8 p8.0 p8.1 p8.2 p8.3 p8.4 p8.5 p8.6 p8.7 p8.8 p8.9 p8.10 p8.11 p8.12 p8.13 p8.14 p8.15 u23 u20 u22 u21 t23 t22 t21 r23 r20 r22 r21 p23 p22 p21 n20 n23 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 8 port 8 is a 16-bit bidirectional general purpose i/o port which also serves as input or output for the gpta. in0 / out0 line of gpta in1 / out1 line of gpta in2 / out2 line of gpta in3 / out3 line of gpta in4 / out4 line of gpta in5 / out5 line of gpta in6 / out6 line of gpta in7 / out7 line of gpta in8 / out8 line of gpta in9 / out9 line of gpta in10 / out10 line of gpta in11 / out11 line of gpta in12 / out12 line of gpta in13 / out13 line of gpta in14 / out14 line of gpta in15 / out15 line of gpta p9 p9.0 p9.1 p9.2 p9.3 p9.4 p9.5 p9.6 p9.7 p9.8 p9.9 p9.10 p9.11 p9.12 p9.13 p9.14 p9.15 n22 n21 m21 m23 m22 l22 l21 l23 l20 k21 k22 k23 j21 j22 j20 j23 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 9 port 9 is a 16-bit bidirectional general purpose i/o port which also serves as input or output for the gpta. in16 / out16 line of gpta in17 / out17 line of gpta in18 / out18 line of gpta in19 / out19 line of gpta in20 / out20 line of gpta in21 / out21 line of gpta in22 / out22 line of gpta in23 / out23 line of gpta in24 / out24 line of gpta in25 / out25 line of gpta in26 / out26 line of gpta in27 / out27 line of gpta in28 / out28 line of gpta in29 / out29 line of gpta in30 / out30 line of gpta in31 / out31 line of gpta table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 14 v1.2, 2002-05 preliminary p10 p10.0 p10.1 p10.2 p10.3 p10.4 p10.5 p10.6 p10.7 p10.8 p10.9 p10.10 p10.11 p10.12 p10.13 p10.14 p10.15 h21 h22 h23 g21 g22 g20 g23 f22 f23 f21 e22 e23 e21 d22 d23 e20 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 10 port 10 is a 16-bit bidirectional general purpose i/o port which also serves as input or output for the gpta. in32 / out32 line of gpta in33 / out33 line of gpta in34 / out34 line of gpta in35 / out35 line of gpta in36 / out36 line of gpta in37 / out37 line of gpta in38 / out38 line of gpta in39 / out39 line of gpta in40 / out40 line of gpta in41 / out41 line of gpta in42 / out42 line of gpta in43 / out43 line of gpta in44 / out44 line of gpta in45 / out45 line of gpta in46 / out46 line of gpta in47 / out47 line of gpta p11 p11.0 p11.1 p11.2 p11.3 p11.4 p11.5 p11.6 p11.7 p11.8 p11.9 p11.10 p11.11 p11.12 p11.13 p11.14 p11.15 c22 c23 c21 b23 a23 a22 b22 d20 a21 b21 c20 d19 a20 b20 c19 a19 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 11 port 11 is a 16-bit bidirectional general purpose i/o port which also serves as input or output for the gpta. in48 / out48 line of gpta in49 / out49 line of gpta in50 / out50 line of gpta in51 / out51 line of gpta in52 / out52 line of gpta in53 / out53 line of gpta in54 / out54 line of gpta in55 / out55 line of gpta in56 / out56 line of gpta in57 / out57 line of gpta in58 / out58 line of gpta in59 / out59 line of gpta in60 / out60 line of gpta in61 / out61 line of gpta in62 / out62 line of gpta in63 / out63 line of gpta table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 15 v1.2, 2002-05 preliminary p12 p12.0 p12.1 p12.2 p12.3 p12.4 p12.5 p12.6 p12.7 p12.8 p12.9 p12.10 p12.11 p12.12 p12.13 p12.14 p12.15 d13 a13 b13 c13 c12 a12 b12 b11 c11 a11 d11 c10 b10 a10 c9 b9 i/o o o o o o o i i i i i o i/o o i/o o port 12 port 12 is a 16-bit bidirectional general purpose i/o port or serves as adc control port and sdlm/asc i/o port. ad0emux0 adc0 external multiplexer control 0 ad0emux1 adc0 external multiplexer control 1 ad0emux2 adc0 external multiplexer control 2 ad1emux0 adc1 external multiplexer control 0 ad1emux1 adc1 external multiplexer control 1 ad1emux2 adc1 external multiplexer control 2 ad1extin0 adc1 external trigger input 0 ad1extin1 adc1 external trigger input 1 ad0extin0 adc0 external trigger input 0 ad0extin1 adc0 external trigger input 1 rxj1850 sdlm receiver input txj1850 sdlm transmitter output rxd0a asc0 receiver input/output a txd0a asc0 transmitter output a rxd1a asc1 receiver input/output a txd1a asc1 transmitter output a table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 16 v1.2, 2002-05 preliminary p13 p13.0 p13.1 p13.2 p13.3 p13.4 p13.5 p13.6 p13.7 p13.8 p13.9 p13.10 p13.11 p13.12 p13.13 p13.14 p13.15 b19 c18 a18 b18 a17 d17 b17 c17 a16 b16 c16 a15 d15 b15 c15 a14 i/o i/o i/o i/o i/o i/o o i/o i/o i/o o i/o i/o i/o i/o i/o i/o i/o i/o i o i o port 13 port 13 is a 16-bit bidirectional general purpose i/o port that is also used as input/output for the serial interfaces (asc, ssc, can) and timers (gptu). gpt0 gptu i/o line 0 gpt1 gptu i/o line 1 gpt2 gptu i/o line 2 rxd0b asc0 receiver input/output b gpt3 gptu i/o line 3 txd0b asc0 transmitter output b gpt4 gptu i/o line 4 rxd1b asc1 receiver input/output b gpt5 gptu i/o line 5 txd1b asc1 transmitter output b gpt6 gptu i/o line 6 sclk0 ssc0 clock input/output gpt7 gptu i/o line 7 mrst0 ssc0 master receive / slave transmit input/output mtsr0 ssc0 master transmit / slave receive output/input sclk1 ssc1 clock input/output mrst1 ssc1 master receive / slave transmit input/output mtsr1 ssc1 master transmit / slave receive output/input rxdcan0 can receiver input 0 txdcan0 can transmitter output 0 rxdcan1 can receiver input 1 txdcan1 can transmitter output 1 clksel0 clksel1 clksel2 v21 v23 v22 i i i pll clock selection inputs these pins are sampled during power-on reset (porst = low); they determine the division rate in the feedback path of the pll (n-factor). the latched values of these input pins are available in the pll clock control register pll_clc. the combination bypass = 1 and clksel[2:0] = 000 b during power-on reset is reserved. table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 17 v1.2, 2002-05 preliminary bypass w22 i pll bypass control input bypass is used for direct drive mode operation of the clock circuitry. this pin is sampled during power-on reset (porst = low). its level is latched into the pll clock control register pll_clc. the combination bypass = 1 and clksel[2:0] = 000 b during power-on reset is reserved. cfg0 cfg1 cfg2 cfg3 y23 y22 w21 w23 i i i i operation configuration inputs the configuration inputs define the boot options of the tc1775 after a hardware reset operation. trst 3) aa19 i jtag module reset/enable input a low level at this pin resets and disables the jtag module. a high level enables the jtag module. tck 3) ab19 i jtag module clock input tdi 4) ac19 i jtag module serial data input tdo aa18 o jtag module serial data output tms 4) ab20 i jtag module state machine control input ocdse 4) y19 i ocds enable input a low level on this pin during power-on reset (porst =low) enables the on-chip debug support (ocds). in addition, the level of this pin during power-on reset determines the boot configuration. brkin 4) ac20 i ocds break input a low level on this pin causes a break in the chip?s execution when the ocds is enabled. in addition, the level of this pin during power-on reset determines the boot configuration. brkout ac18 o ocds break output a low level on this pin indicates that a programmable ocds event has occurred. nmi 4) y20 i non-maskable interrupt input a high-to-low transition on this pin causes a nmi-trap request to the cpu. table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 18 v1.2, 2002-05 preliminary hdrst 4) w20 i/o hardware reset input/reset indication output assertion of this bidirectional open-drain pin causes a synchronous reset of the chip through external circuitry. this pin must be driven for a minimum duration. the internal reset circuitry drives this pin in response to a power-on, hardware, watchdog and power-down wake-up reset for a specific period of time. for a software reset, activation of this pin is programmable. porst 5) y21 i power-on reset input a low level on porst causes an asynchronous reset of the entire chip. porst is a fully asynchronous level sensitive signal. clkin t1 i ebu clock input clkin must be connected externally with clkout. for fine- tuning of the external bus interface timing, this external connection can be an external delay circuit. clkout r1 o clock output test mode 4) ab23 i test mode select input for normal operation of the tc1775, this pin should be connected to v ddp05 . xtal1 xtal2 ac23 ac22 i o oscillator/pll/clock generator input/output pins xtal1 is the input to the main oscillator amplifier and input to the internal clock generator. xtal2 is the output of the main oscillator amplifier circuit. for clocking the device from an external source, xtal1 is driven with the clock signal while xtal2 is left unconnected. for crystal oscillator operation xtal1 and xtal2 are connected to the crystal with the appropriate recommended oscillator circuitry. xtal3 xtal4 ab21 aa20 i o real time clock oscillator input/output xtal3 and xtal4 are the input and the output of the 32 khz oscillator that is used for the real time clock. table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 19 v1.2, 2002-05 preliminary v ddosc ac21 ? main oscillator power supply (2.5 v) 6)7) v ssosc aa21 ? main oscillator ground v ddpll aa22 ? pll power supply (2.5 v) 6)7) v sspll aa23 ? pll ground v ss f4, y6, v20, d18, k10 to k14, l10 to l14, m10 to m14, n10 to n14, p10 to p14 ? ground v dd k4, p4 v4, d6 y10 d14 y18 f20 k20 p20 ? core power supply (2.5 v) 6)7) table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 20 v1.2, 2002-05 preliminary v ddp05 h4 m4 t4 y8 y12 ? ports 0 to 5 power supply (2.5 v ) 6)7) v ddp813 d8 d12 d16 h20 m20 t20 ? port 8-13 and dedicated pins power supply (3.3 to 5 v) 8) v ddsram ac17, ab18 ? sram (rams of dmu, pmu, and pcp) power supply (2.5 v) 7) v ddsb b14 ? stand-by power supply of 8 kbyte sbsram (2.5 v) 7) v ddsc a1 ? adc short circuit/broken wire logic power supply (5 v) 8) v sssc a2 ? adc short circuit/broken wire logic ground v ddm c3 ? adc analog part power supply (5 v) 8) v ssm a3 ? adc analog part ground v dda0 d9 ? adc0 analog part power supply (2.5 v) 6)7) v ssa0 a9 ? adc0 analog part ground for v dda0 v dda1 h1 ? adc1 analog part power supply (2.5 v) 6)7) v ssa1 g3 ? adc1 analog part ground for v dda1 v aref0 c8 ? adc0 reference voltage 8) v agnd0 b8 ? adc0 reference ground v aref1 g2 ? adc1 reference voltage 8) v agnd1 g4 ? adc1 reference ground table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 21 v1.2, 2002-05 preliminary n.c.1 ab15, d10, y14 ? not connected 1 these pins must not be connected. n.c.2 ab22, c14, k3, ac3, l4, d21, y16 ? not connected 2 for compatibility reasons, these pins should not be connected. any connection to 5 v does not harm the device. 1) after reset, an internal pull-up device is enabled for this pin. 2) after reset, an internal pull-down device is enabled for this pin. 3) these pins have an internal pull-down device connected. 4) these pins have an internal pull-up device connected. 5) the tc1775 ba11 step has an internal pull-up device connected to this pin. 6) the voltage on power supply pins marked with 8) has to be raised earlier or at least at the same time as on power supply pins marked with 6) (details see power supply section on page 62 ). 7) in order to minimize the danger of latch-up conditions, these 2.5 v v dd power supply pins should be kept at the same voltage level during normal operating mode. this condition is best achieved by generating the 2.5 v power supplies from a single voltage source. the condition is also valid in normal operating mode if a separate stand-by power supply v ddsb is used. 8) the voltage on power supply pins marked with 8) has to be raised earlier or at least at the same time as on power supply pins marked with 6) (details see power supply section on page 62 ). table 1 pin definitions and functions (cont?d) symbol pin in out functions
tc1775 data sheet 22 v1.2, 2002-05 preliminary parallel ports the tc1775 has 196 digital input/output port lines, which are organized into twelve parallel 16-bit ports, port 0 to port 5 with 2.5 v nominal voltage (pin class b), and port 8 to port 13 with 3.0 to 5.25 v voltage (pin class a). additionally, 32 analog input port lines are available, which are organized into two parallel 16-bit ports, port 6 and port 7. the digital parallel ports can be all used as general purpose i/o lines or they can perform input/output functions for the on-chip peripheral units. port 0 to port 5 are especially dedicated for the on-chip external bus interface unit to communicate with external memories, external peripherals, or external debugging devices via an external bus interface. port 8 to port 13 can be assigned to the on-chip peripheral units for their specific i/o operations. an overview on the port-to-peripheral unit assignment is shown in figure 4 . note: for further details on the three pin classes of the tc1775 i/o pins see also table 10 on page 64 : figure 4 parallel ports of the tc1775 mca04734 tc 1775 parallel ports port 8 port 9 port 10 port 11 port 12 port 13 g pio alternate functions gpta gpta gpta gpta adc0/1 / asc0/1 / sdlm ssc0/1 / asc0/1 / gptu / can port 1 port 0 port 2 port 3 port 4 port 5 gpio alternate functions ocds trace lines bus control lines address bus bus control lines address bus address/data bus address/data bus adc0 adc1 port 6 port 7
tc1775 data sheet 23 v1.2, 2002-05 preliminary serial interfaces the tc1775 includes six serial peripheral interface units: ? two asynchronous/synchronous serial interfaces (asc0 and asc1) ? two high-speed synchronous serial interfaces (ssc0 and ssc1) ? one twincan interface ? one j1850 serial data link interface (sdlm) asynchronous/synchronous serial interfaces figure 5 shows a global view of the functional blocks of the two asynchronous/ synchronous serial interfaces asc0 and asc1. figure 5 general block diagram of the asc interfaces mcb04485 clock control address decoder interrupt control f asc0 asc0 module (kernel) port 12 & port 13 control p12.12 / rxd0a rxd0 txd0 p12.13 / txd0a p13.3 / txd0b p13.2 / rxd0b clock control address decoder interrupt control f asc1 asc1 module (kernel) rxd1 txd1 p12.14 / rxd1a p12.15 / txd1a p13.5 / txd1b p13.4 / rxd1b
tc1775 data sheet 24 v1.2, 2002-05 preliminary each asc module, asc0 and asc1, communicates with the external world via two pairs of two i/o lines each. the rxd line is the receive data input signal (in synchronous mode also output). txd is the transmit output signal. clock control, address decoding, and interrupt service request control are managed outside the asc module kernel. the asynchronous/synchronous serial interfaces provide serial communication between the tc1775 and other microcontrollers, microprocessors or external peripherals. the asc supports full-duplex asynchronous communication and half-duplex synchronous communication. in synchronous mode, data is transmitted or received synchronous to a shift clock which is generated by the asc internally. in asynchronous mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. parity, framing, and overrun error detection are provided to increase the reliability of data transfers. transmission and reception of data are double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is supported by a loop-back option. a 13-bit baud rate generator provides the asc with a separate serial clock signal that can be very accurately adjusted by a prescaler implemented as a fractional divider. features: full duplex asynchronous operating modes ? 8-bit or 9-bit data frames, lsb first ? parity bit generation/checking ? one or two stop bits ? baud rate from 2.5 mbit/s to 0.6 bit/s (@ 40 mhz clock) ? multiprocessor mode for automatic address/data byte detection ? loop-back capability half-duplex 8-bit synchronous operating mode ? baud rate from 5 mbit/s to 406.9 bit/s (@ 40 mhz clock) double buffered transmitter/receiver interrupt generation ? on a transmitter buffer empty condition ? on a transmit last bit of a frame condition ? on a receiver buffer full condition ? on an error condition (frame, parity, overrun error) two pin pairs rxd/txd for each asc available at port 12 or port 13
tc1775 data sheet 25 v1.2, 2002-05 preliminary high-speed synchronous serial interfaces figure 6 shows a global view of the functional blocks of the two high-speed synchronous serial interfaces ssc0 and ssc1. figure 6 general block diagram of the ssc interfaces each of the ssc modules has three i/o lines, located at port 13. each of the ssc modules is further supplied by separate clock control, interrupt control, address decoding, and port control logic. the ssc supports full-duplex and half-duplex serial synchronous communication up to 20 mbit/s (@ 40 mhz module clock). the serial clock signal can be generated by the ssc itself (master mode) or can be received from an external master (slave mode). data width, shift direction, clock polarity, and phase are programmable. this allows communication with spi-compatible devices. transmission and reception of data are double-buffered. a 16-bit baud rate generator provides the ssc with a separate serial clock signal. mcb04486 clock control address decoder interrupt control f ssc0 ssc0 module (kernel) port control p13.8 / mtsr0 p13.7 / mrst0 p13.6 / sclk0 clock control address decoder interrupt control f ssc1 ssc1 module (kernel) rxd txd master rxd txd slave slave master sclk p13.11 / mtsr1 p13.10 / mrst1 p13.9 / sclk1 rxd txd master rxd txd slave slave master sclk
tc1775 data sheet 26 v1.2, 2002-05 preliminary features: master and slave mode operation ? full-duplex or half-duplex operation flexible data format ? programmable number of data bits: 2 to 16 bit ? programmable shift direction: lsb or msb shift first ? programmable clock polarity: idle low or high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock baud rate generation from 20 mbit/s to 305.18 bit/s (@ 40 mhz module clock) interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baud rate, transmit error) three-pin interface ? flexible ssc pin configuration
tc1775 data sheet 27 v1.2, 2002-05 preliminary twincan interface figure 7 shows a global view of the functional blocks of the twincan module. figure 7 general block diagram of the twincan module the twincan module has four i/o lines located at port 13. the twincan module is further supplied by a clock control, interrupt control, address decoding, and port control logic. the twincan module contains two full-can nodes operating independently or exchanging data and remote frames via a gateway function. transmission and reception of can frames are handled in accordance to can specification v2.0 part b (active). each of the two full-can interfaces can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. both can nodes share the twincan module?s resources to optimize the can bus traffic handling and to minimize the cpu load. the flexible combination of full-can functionality and the fifo architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. improved can bus monitoring functionality as well as the increased number of message objects permit precise and convenient can bus traffic handling. depending on the application, each of the thirty-two message objects can be individually assigned to one of the two can nodes. gateway functionality allows automatic data exchange between two separate can bus systems to reduce cpu load and improve the real time behavior of the entire system. mcb04674 clock control address decoder interrupt control sr1 sr2 f can sr3 sr0 twincan module kernel port control p13.13 / txdcan0 p13.12 / rxdcan0 sr7 sr6 sr5 p13.15 / txdcan1 p13.14 / rxdcan1 bitstream processor interrupt control sr4 txdc0 rxdc0 txdc1 rxdc1 timing control error handling control message buffers
tc1775 data sheet 28 v1.2, 2002-05 preliminary the bit timings for both can nodes are derived from the peripheral clock ( f can ) and are programmable up to a data rate of 1 mbit/s. a pair of receive and transmit pins connect each can node to a bus transceiver. features: full can functionality conforms to can specification v2.0 b active dedicated control registers are provided for each can node a data transfer rate up to 1 mbit/s is supported flexible and powerful message transfer control and error handling capabilities are implemented full-can functionality: 32 message objects can be individually ? assigned to one of the two can nodes ? configured as transmit or receive objects ? participate in a 2, 4, 8, 16 or 32 message buffer with fifo algorithm ? setup to handle frames with 11-bit or 29-bit identifiers ? provided with programmable acceptance mask register for filtering ? monitored via a frame counter ? configured to remote monitoring mode up to eight individually programmable interrupt nodes can be used can analyzer mode for bus monitoring is implemented
tc1775 data sheet 29 v1.2, 2002-05 preliminary serial data link interface figure 8 shows a global view of the functional blocks of the serial data link interface (sdlm). figure 8 general block diagram of the sdlm interface the sdlm module communicates with the external world via two i/o lines located at port 12, the j1850 bus. the rxd line is the receive data input signal and txd is the transmit data output signal. the serial data link module (sdlm) provides serial communication to a j1850 based serial bus. j1850 bus transceivers must be implemented externally in a system. the sdlm module conforms to the sae class b j1850 specification and is compatible to class 2 protocol. general sdlm features: compliant to sae class b j1850 specification full support of gm class 2 protocol variable pulse width (vpw) format with 10.4 kbit/s high speed receive/transmit 4x mode with 41.6 kbit/s digital noise filter support of single byte headers or consolidated headers crc generation and check support of block mode for receive and transmit mcb04570 clock control address decoder interrupt control f sdlm sdlm module (kernel) port control p12.10 / rxj1850 rxd txd p12.11 / txj1850
tc1775 data sheet 30 v1.2, 2002-05 preliminary data link operation features: 11-byte transmit buffer double buffered 11-byte receive buffer support of in-frame response (ifr) types 1, 2, 3 advanced interrupt handling for rx, tx, and error conditions all interrupt sources can be enabled/disabled individually support of automatic ifr transmission for ifr types 1 and 2 for 3-byte consolidated headers note: the sdlm module does not support the pulse width modulation (pwm) data format.
tc1775 data sheet 31 v1.2, 2002-05 preliminary timer units the tc1775 includes two timer units: ? general purpose timer unit (gptu) ? general purpose timer array (gpta) general purpose timer unit figure 9 shows a global view of all functional blocks of the general purpose timer unit (gptu) module. figure 9 general block diagram of the gptu interface the gptu consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. the gptu communicates with the external world via eight inputs and eight outputs located at port 13. the three timers of the gptu module (t0, t1, and t2) can operate independently from each other, or can be combined: general features: all timers are 32-bit precision timers with a maximum input frequency of f gptu events generated in t0 or t1 can be used to trigger actions in t2 timer overflow or underflow in t2 can be used to clock either t0 or t1 t0 and t1 can be concatenated to form one 64-bit timer mcb04489 clock control address decoder interrupt control sr1 sr2 f gptu sr3 sr0 gptu module (kernel) port control p13.1 / gpt1 sr7 sr6 sr5 sr4 in 1 in 2 in 3 in 0 in 7 in 6 in 5 in 4 out0 out1 out2 out3 out4 out5 out6 out7 io 1 p13.7 / gpt7 io 7 io 0 p13.0 / gpt0 io 2 p13.2 / gpt2 io 3 p13.3 / gpt3 p13.4 / gpt4 io 4 io 5 p13.5 / gpt5 io 6 p13.6 / gpt6
tc1775 data sheet 32 v1.2, 2002-05 preliminary features of t0 and t1: each timer has a dedicated 32-bit reload register with automatic reload on overflow timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers overflow signals can be selected to generate service requests, pin output signals, and t2 trigger events two input pins can define a count option features of t2: count up or down is selectable operating modes: ?timer ? counter ? quadrature counter (incremental/phase encoded counter interface) options: ? external start/stop, one-shot operation, timer clear on external event ? count direction control through software or an external event ? two 32-bit reload/capture registers reload modes: ? reload on overflow or underflow ? reload on external event: positive transition, negative transition, or both transitions capture modes: ? capture on external event: positive transition, negative transition, or both transitions ? capture and clear timer on external event: positive transition, negative transition, or both transitions can be split into two 16-bit counter/timers timer count, reload, capture, and trigger functions can be assigned to input pins. t0 and t1 overflow events can also be assigned to these functions overflow and underflow signals can be used to trigger t0 and/or t1 and to toggle output pins t2 events are freely assignable to the service request nodes
tc1775 data sheet 33 v1.2, 2002-05 preliminary general purpose timer array figure 10 shows a global block diagram of the general purpose timer array (gpta) implementation. figure 10 gpta module block diagram the gpta module has 64 input lines and 64 output lines, which are connected with port 8, port 9, port 10, and port 11. the general purpose timer array (gpta) provides important digital signal filtering and timer support whose combination enables autonomous and complex functionalities. this architecture allows easy implementation and easy validation of any kind of timer functions. mcb04490 clock control address decoder a/d converter ptin01 ptin10 f gpta ptin11 ptin00 interrupt control sr01 sr52 sr53 sr00 port control io 62 io 63 p11.0 p11.1 p11.14 p11.15 gpta module kernel clock generation unit filter & prescaler cells phase discrim inator logic duty cycle measurement digital phase locked loop interrupt control unit io sharing unit with emergency shut-off signal generation unit global timers global timer cells local timer cells out62 out63 io 48 io 49 io 46 io 47 p10.0 p10.1 p10.14 p10.15 io 32 io 33 io 30 io 31 p9.0 p9.1 p9.14 p9.15 io 16 io 17 io 14 io 15 p8.0 p8.1 p8.14 p8.15 io 0 io 1 in0 in1 out0 out1 in 63 in 62 as0 as1 as62 as63
tc1775 data sheet 34 v1.2, 2002-05 preliminary the general purpose timer array (gpta) provides a set of hardware modules required for high speed digital signal processing: filter and prescaler cells (fpc) support input noise filtering and prescaler operation. phase discrimination logic units (pdl) decode the direction information output by a rotation tracking system. duty cycle measurement cells (dcm) provide pulse width measurement capabilities. a digital phase locked loop unit (pll) generates a programmable number of gpta module clock ticks during an input signal?s period. global timer units (gt) driven by various clock sources are implemented to operate as a time base for the associated ?global timer cells?. global timer cells (gtc) can be programmed to capture the contents of a global timer on an event that occurred at an external port pin or at an internal fpc output. a gtc may be also used to control an external port pin with the result of an internal compare operation. gtcs can be logically concatenated to provide a common external port pin with a complex signal waveform. local timer cells (ltc) operating in timer, capture, or compare mode may be also logically tied together to drive a common external port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mode ? can be clocked or triggered by ? a prescaled gpta module clock, ? an fpc, pdl, dcm, pll, or gtc output signal line, ? an external port pin. some input lines driven by processor i/o pads may be shared by an ltc and a gtc to trigger their programmed operation simultaneously. the following list summarizes all blocks supported: clock generation unit (gpta) filter and prescaler cell (fpc): ? six independent units ? three operating modes (prescaler, delayed debounce filter, immediate debounce filter) ? f gpta down-scaling capability ? f gpta /2 maximum input signal frequency in filter mode phase discriminator logic (pdl): ? two independent units ? two operating modes (2 and 3 sensor signals) ? f gpta /4 maximum input signal frequency in 2-sensor mode, f gpta /6 maximum input signal frequency in 3-sensor mode duty cycle measurement (dcm): ? four independent units ? 0 to 100% margin and time-out handling
tc1775 data sheet 35 v1.2, 2002-05 preliminary ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency digital phase locked loop (pll): ? one unit ? arbitrary multiplication factor between 1 and 65535 ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency gpta signal generation unit global timers (gt): ? two independent units ? two operating modes (free running timer and reload timer) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency global timer cell (gtc): ? 32 independent units ? two operating modes (capture, compare and capture after compare) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency local timer cell (ltc): ? 64 independent units ? three operating modes (timer, capture and compare) ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency interrupt control unit 111 interrupt sources generating 54 service requests i/o sharing unit able to process lines from fpc, gtc, and ltc emergency function
tc1775 data sheet 36 v1.2, 2002-05 preliminary analog digital converters the two on-chip analog-to-digital converter (adc) modules of the tc1775 offer 8-bit, 10-bit, or 12-bit resolution including sample-and-hold functionality. the a/d converters operate using the method of the successive approximation. a multiplexer selects among up to 16 analog input channels for each adc. conversion requests are generated either under software control or by hardware. an automatic self-calibration adjusts the adc modules to changing temperatures or process variations. features: 8-bit, 10-bit, 12-bit a/d conversion successive approximation conversion method fast conversion times: e.g. 10-bit conversion (without sample time): 5.05 s total unadjusted error (tue) of 2 lsb @ 10-bit resolution integrated sample-and-hold functionality sixteen analog input channels dedicated control and status registers for each analog channel powerful conversion request sources selectable reference voltages for each channel programmable sample and conversion timing schemes limit checking broken wire ? short circuit detection flexible service request generation synchronization of the two on-chip a/d converters automatic control of external analog multiplexer equidistant samples initiated by timer external trigger inputs for conversion requests two external trigger inputs, connected with the general purpose timer array (gpta) power reduction and clock control figure 11 shows a global view of the adc module kernels with the module specific interface connections. each of the adc modules communicates with the external world via five digital i/o lines and sixteen analog inputs. clock control, address decoding, and interrupt service request control are managed outside the adc module kernel. two trigger inputs and a synchronization bridge are used for internal control purposes.
tc1775 data sheet 37 v1.2, 2002-05 preliminary figure 11 adc0/adc1 modules with interconnections mcb04491 clock control address decoder interrupt control sr1 sr2 f adc0 sr3 gpta ptin00 sr0 ptin01 adc0 module kernel synchronization bridge adc1 module kernel ptin10 ptin11 clock control address decoder interrupt control sr1 sr2 f adc1 sr3 sr0 port control p12.8 / ad0extin0 p12.9 / ad0extin1 p12.0 / ad0emux0 p12.1 / ad0emux1 p12.2 / ad0emux2 p6.0 / an0 p6.1 / an1 p6.14 / an14 p6.15 / an15 port control p12.6 / ad1extin0 p12.7 / ad1extin1 p12.3 / ad1emux0 p12.4 / ad1emux1 p12.5 / ad1emux2 p7.0 / an16 p7.1 / an17 p7.14 / an30 p7.15 / an31 v agnd0 v ssa0 v dda0 v ddm v aref0 v ssm v agnd1 v ssa1 v dda1 v ddm v aref1 v ssm ain15 ain14 ain0 ain1 ain15 ain14 ain0 ain1
tc1775 data sheet 38 v1.2, 2002-05 preliminary on-chip memories the memory system of the tc1775 provides the following memories: program memory unit (pmu) with ? 8 kbytes boot rom (brom) ? 32 kbytes code scratch-pad ram (spram) ? 1 kbyte instruction cache (icache) data memory unit (dmu) with ? 40 kbytes data memory (sram) ? includes 8 kbytes static ram (sbsram) for standby operation using a battery peripheral control processor (pcp) with ? 16 kbytes data memory (pcode) ? 4 kbytes parameter ram (pram)
tc1775 data sheet 39 v1.2, 2002-05 preliminary address map table 2 defines the specific segment oriented address blocks of the tc1775 with its address range, size, and pmu/dmu access view. table 3 shows the block address map of memory segment 15 which includes the on-chip peripheral units. table 2 tc1775 block address map seg- ment address range size description dmu acc. pmu acc. 1) 0 to 7 0000 0000 h ? 7fff ffff h 2 gb reserved ? ? 8 8000 0000 h ? 8fff ffff h 256 mb reserved via fpi pmu local cached 9 9000 0000 h ? 9fff ffff h 256 mb reserved dmu local via fpi 10 a000 0000 h ? afff ffff h 256 mb external memory space via fpi via ebu or fpi 11 b000 0000 h ? bdff ffff h 224 mb external memory space mappable into segment 10 via fpi via ebu non-cached be00 0000 h ? beff ffff h 16 mb external emulator space via fpi bf00 0000 h ? bfff dfff h ? reserved pmu local bfff e000 h ? bfff ffff h 8 kb boot rom 4 kbytes general purpose 4 kbytes factory test support 12 c000 0000 h ? c000 7fff h 32 kb local code scratch-pad ram (spram) via fpi pmu local c000 8000 h ? c7ff feff h ? reserved c7ff ff00 h ? c7ff ffff h 256 b pmu control registers c800 0000 h ? cfff ffff h 128 mb reserved
tc1775 data sheet 40 v1.2, 2002-05 preliminary 13 d000 0000 h ? d000 7fff h 32 kb local data memory (sram) dmu local via fpi non-cached d000 8000 h ? d000 9fff h 8 kb local data memory for standby operation (sbsram) d000 a000 h ? d000 bfff h 8 kb sbsram mirrored d000 c000 h ? d000 dfff h 8 kb sbsram mirrored d000 e000 h ? d000 ffff h 8 kb sbsram mirrored d000 a000 h ? d7ff feff h ? reserved d7ff ff00 h ? d7ff ffff h 256 b dmu registers d800 0000 h ? dfff ffff h 256 mb reserved 14 e000 0000 h ? efff ffff h 256 mb external peripheral and data memory space via fpi not possi- ble table 2 tc1775 block address map (cont?d) seg- ment address range size description dmu acc. pmu acc. 1)
tc1775 data sheet 41 v1.2, 2002-05 preliminary 15 f000 0000 h ? f000 3eff h 16 kb on-chip peripherals & ports via fpi not possi- ble non-cached f000 3f00 h ? f000 3fff h 256 b pcp registers f000 4000 h ? f000 ffff h ? reserved f001 0000 h ? f001 0fff h 4 kb pcp parameter memory (pram) f001 1000 h ? f001 ffff h ? reserved f002 0000 h ? f002 3fff h 16 kb pcp code memory (pcode) f002 4000 h ? f00f ffff h ? reserved f010 0000 h ? f010 0bff h 12 256 b can module f010 0c00 h ? fffe feff h ? reserved fffe ff00 h ? fffe ffff h 256 b cpu slave interface registers (cps) ffff 0000 h ? ffff ffff h 64 kb core sfrs + gprs 1) the pmu can access external memory directly (?via ebu?, only instruction accesses) or via the fpi bus (?via fpi?). table 2 tc1775 block address map (cont?d) seg- ment address range size description dmu acc. pmu acc. 1)
tc1775 data sheet 42 v1.2, 2002-05 preliminary table 3 block address map of segment 15 symbol description address range size scu system control unit f000 0000 h ? f000 00ff h 256 bytes rtc real time clock f000 0100 h ? f000 01ff h 256 bytes bcu bus control unit f000 0200 h ? f000 02ff h 256 bytes stm system timer f000 0300 h ? f000 03ff h 256 bytes ocds on-chip debug support f000 0400 h ? f000 04ff h 256 bytes ebu external bus unit f000 0500 h ? f000 05ff h 256 bytes ? reserved f000 0600 h ? f000 06ff h ? gptu general purpose timer unit f000 0700 h ? f000 07ff h 256 bytes asc0 async./sync. serial interface 0 f000 0800 h ? f000 08ff h 256 bytes asc1 async./sync. serial interface 1 f000 0900 h ? f000 09ff h 256 bytes ssc0 high-speed synchronous serial interface 0 f000 0a00 h ? f000 0aff h 256 bytes ssc1 high-speed synchronous serial interface 1 f000 0b00 h ? f000 0bff h 256 bytes ? reserved f000 0c00 h ? f000 17ff h ? gpta general purpose timer array f000 1800 h ? f000 1fff h 8 256 bytes ? reserved f000 2000 h ? f000 21ff h ? adc0 analog-to-digital converter 0 f000 2200 h ? f000 23ff h 512 bytes adc1 analog-to-digital converter 1 f000 2400 h ? f000 25ff h 512 bytes sdlm serial data link module f000 2600 h ? f000 26ff h 256 bytes ? reserved f000 2700 h ? f000 27ff h ? p0 port 0 f000 2800 h ? f000 28ff h 256 bytes p1 port 1 f000 2900 h ? f000 29ff h 256 bytes p2 port 2 f000 2a00 h ? f000 2aff h 256 bytes p3 port 3 f000 2b00 h ? f000 2bff h 256 bytes p4 port 4 f000 2c00 h ? f000 2cff h 256 bytes p5 port 5 f000 2d00 h ? f000 2dff h 256 bytes p6 port 6 (no registers available) f000 2e00 h ? f000 2eff h 256 bytes p7 port 7 (no registers available) f000 2f00 h ? f000 2fff h 256 bytes p8 port 8 f000 3000 h ? f000 30ff h 256 bytes p9 port 9 f000 3100 h ? f000 31ff h 256 bytes
tc1775 data sheet 43 v1.2, 2002-05 preliminary p10 port 10 f000 3200 h ? f000 32ff h 256 bytes p11 port 11 f000 3300 h ? f000 33ff h 256 bytes p12 port 12 f000 3400 h ? f000 34ff h 256 bytes p13 port 13 f000 3500 h ? f000 35ff h 256 bytes ? reserved f000 3600 h ? f000 3eff h ? pcp pcp registers f000 3f00 h ? f000 3fff h 256 bytes reserved f000 4000 h ? f000 ffff h ? pcp data memory (pram) f001 0000 h ? f001 0fff h 4 kbytes reserved f001 1000 h ? f001 ffff h ? pcp code memory (pcode) f002 0000 h ? f002 3fff h 16 kbytes ? reserved f002 4000 h ? f00f ffff h ? can 1) controller area network module f010 0000 h ? f010 0bff h 12 256 bytes ? reserved f010 0c00 h ? fffe feff h ? cpu slave interface registers (cps) fffe ff00 h ? fffe ffff h 256 bytes reserved ffff 0000 h ? ffff bfff h ? memory protection registers ffff c000 h ? ffff efff h 12 kbytes reserved ffff f000 h ? ffff fcff h ? core debug register (ocds) ffff fd00 h ? ffff fdff h 256 bytes core special function registers (csfrs) ffff fe00 h ? ffff feff h 256 bytes general purpose register (gprs) ffff ff00 h ? ffff ffff h 256 bytes 1) access to unused address regions within this peripheral unit don?t generate a bus error. table 3 block address map of segment 15 (cont?d) symbol description address range size
tc1775 data sheet 44 v1.2, 2002-05 preliminary memory protection system the tc1775 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. the memory protection system controls the position and range of addressable segments in memory. it also controls the kinds of read and write operations allowed within addressable memory segments. any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate trap service routine (tsr) to handle the error. thus, the memory protection system protects critical system functions against both software and hardware errors. the memory protection hardware can also generate signals to the debug unit to facilitate tracing illegal memory accesses. there are two memory protection register sets in the tc1775, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. the psw.prs bit field determines which of these is the set currently in use by the cpu. because the tc1775 uses a harvard-style memory architecture, each memory protection register set is broken down into a data protection register set and a code protection register set. each data protection register set can specify up to four address ranges to receive particular protection modes. each code protection register set can specify up to two address ranges to receive particular protection modes. each of the data protection register sets and code protection register sets determines the range and protection modes for a separate memory area. each contains register pairs which determine the address range (the data segment protection registers and code segment protection registers) and one register (data protection mode register) which determines the memory access modes which apply to the specified range.
tc1775 data sheet 45 v1.2, 2002-05 preliminary on-chip fpi bus the fpi bus interconnects the functional units of the tc1775, such as the cpu and on-chip peripheral components. the fpi bus also interconnects the tc1775 to external components by way of the external bus controller unit (ebu). the fpi bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. the low setup overhead of the fpi bus access protocol guarantees fast fpi bus acquisition, which is required for time-critical applications. the fpi bus is designed to sustain high transfer rates. for example, a peak transfer rate of up to 160 mbyte/s can be achieved with a 40 mhz bus clock and 32-bit data bus. multiple data transfers per bus arbitration cycle allow the fpi bus to operate at close to its peak bandwidth. features: supports multiple bus masters supports demultiplexed address/data operation address and data buses are 32 bits wide data transfer types include 8-, 16-, and 32-bit sizes single- and multiple-data transfers per bus acquisition cycle designed to minimize emi and power consumption
tc1775 data sheet 46 v1.2, 2002-05 preliminary external bus unit the external bus unit (ebu) of the tc1775 is the interface between external memories and peripheral units and the internal memories and peripheral units. the basic structure of the ebu is shown in figure 12 . figure 12 ebu structure and interfaces the ebu is primarily used for the following two operations: communication with external memories or peripheral units via the fpi bus instruction fetches from the pmu to external burst flash program memories the ebu controls all transactions required for these two operations and in particular handles the arbitration between these two tasks. the types of external devices/bus modes controlled by the ebu are: intel style peripherals (separate rd and wr signals) roms, eproms static rams demultiplexed a/d bus multiplexed a/d bus the pmu controls accesses to external code memories. it especially supports: ? burst mode flash memories (rom) note: instruction fetches of the pmu from external burst flash program memories are only possible with 32-bit data bus width. mca04753 tricore cpu pmu with on-chip program memory dmu with on-chip data m em ory ebu port 4 port 3 port 2 port 1 port 0 control lines a[25:16] and chip select a[15:0] ad[31:16] ad[15:0] fpi bus burst mode instruction fetches to peripheral units and pcp
tc1775 data sheet 47 v1.2, 2002-05 preliminary peripheral control processor the peripheral control processor (pcp) performs tasks that would normally be performed by the combination of a dma controller and its supporting cpu interrupt service routines in a traditional computer system. it could easily be considered as the host processor?s first line of defense as an interrupt-handling engine. the pcp can off- load the cpu from having to service time-critical interrupts. this provides many benefits, including: avoiding large interrupt-driven task context-switching latencies in the host processor lessening the cost of interrupts in terms of processor register and memory overhead improving the responsiveness of interrupt service routines to data-capture and data- transfer operations easing the implementation of multitasking operating systems. the pcp has an architecture that efficiently supports dma type transactions to and from arbitrary devices and memory addresses within the tc1775 and also has reasonable stand alone computational capabilities. the pcp is made up of several modular blocks as follows: pcp processor core code memory (pcode) parameter memory (pram) pcp interrupt control unit (picu) pcp service request nodes (psrn) system bus interface to the fpi bus the pcp is fully interrupt-driven, meaning it is only activated through service requests; there is no main program running in the background as with a conventional processor.
tc1775 data sheet 48 v1.2, 2002-05 preliminary figure 13 pcp block diagram table 4 pcp instruction set overview instruction group description dma primitives efficient dma channel implementation load/store transfer data between pram or fpi memory and the general purpose registers, as well as move or exchange values between registers arithmetic add, subtract, compare and complement divide/multiply divide and multiply logical and, or, exclusive or, negate shift shift right or left, rotate right or left, prioritize bit manipulation set, clear, insert and test bits flow control jump conditionally, jump long, exit miscellaneous no operation, debug mcb04784 pcp processor core pcp service req. nodes psrns pcp interrupt control unit picu parameter memory pram code memory pcode fpi-interface pcp interrupt arbitration bus cpu interrupt arbitration bus fpi bus
tc1775 data sheet 49 v1.2, 2002-05 preliminary system timer the stm within the tc1775 is designed for global system timing applications requiring both high precision and long range. the stm provides the following features: free-running 56-bit counter all 56 bits can be read synchronously different 32-bit portions of the 56-bit counter can be read synchronously driven by clock f stm (identical with the system clock f sys ) counting begins at power-on reset continuous operation is not affected by any reset condition except power-on reset the stm is an upward counter, running with the system clock frequency f sys . it is enabled per default after reset, and immediately starts counting up. other than via reset, it is not possible to affect the contents of the timer during normal operation of the application, it can only be read, but not written to. depending on the implementation of the clock control of the stm, the timer can optionally be disabled or suspended for power-saving and debugging purposes via a clock control register. the maximum clock period is 2 56 1/ f stm . at f stm = 40 mhz, for example, the stm counts 57.1 years before overflowing. thus, it is capable of continuously timing the entire expected product life-time of a system without overflowing. figure 14 block diagram of the stm module stm module 00 h cap tim6 tim5 tim4 tim3 tim2 tim1 tim0 00 h 55 47 39 31 23 15 7 56-bit system timer address decoder clock control enable/ disable porst f stm mca04795
tc1775 data sheet 50 v1.2, 2002-05 preliminary watchdog timer the watchdog timer (wdt) provides a highly reliable and secure way to detect and recover from software or hardware failure. the wdt helps to abort an accidental malfunction of the tc1775 in a user-specified time period. when enabled, the wdt will cause the tc1775 system to be reset if the wdt is not serviced within a user- programmable time period. the cpu must service the wdt within this time interval to prevent the wdt from causing a tc1775 system reset. hence, routine service of the wdt confirms that the system is functioning properly. in addition to this standard ?watchdog? function, the wdt incorporates the endinit feature and monitors its modifications. a system-wide line is connected to the endinit bit implemented in a wdt control register, serving as an additional write-protection for critical registers (besides supervisor mode protection). a further enhancement in the tc1775?s watchdog timer is its reset prewarning operation. instead of immediately resetting the device on the detection of an error, as known from standard watchdogs, the wdt first issues an non-maskable interrupt (nmi) to the cpu before finally resetting the device at a specified time period later. this gives the cpu a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging. features: 16-bit watchdog counter selectable input frequency: f sys /256 or f sys /16384 16-bit user-definable reload value for normal watchdog operation, fixed reload value for time-out and prewarning modes incorporation of the endinit bit and monitoring of its modifications sophisticated password access mechanism with fixed and user-definable password fields proper access always requires two write accesses. the time between the two accesses is monitored by the wdt and limited. access error detection: invalid password (during first access) or invalid guard bits (during second access) trigger the watchdog reset generation. overflow error detection: an overflow of the counter triggers the watchdog reset generation. watchdog function can be disabled; access protection and endinit monitor function remain enabled. double reset detection: if a watchdog induced reset occurs twice without a proper access to its control register in between, a severe system malfunction is assumed and the tc1775 is held in reset until a power-on reset. this prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed.
tc1775 data sheet 51 v1.2, 2002-05 preliminary important debugging support is provided through the reset prewarning operation by first issuing an nmi to the cpu before finally resetting the device after a certain period of time. real time clock figure 15 shows a global view of all functional blocks oft he rtc interface. figure 15 block diagram of the rtc interface the real time clock (rtc) module is an independent timer chain that counts time ticks. the base frequency of the rtc can be programmed via a reload counter. the rtc can work asynchronously with the system frequency, and is optimized on low power consumption. features: on-chip 32.768 khz oscillator for counting current time and date cyclic time-based interrupts alarm interrupt for wake-up on a defined time 48-bit timer for long-term measurements mcb04808 rtc o scillator scu address decoder f rtc_count rtc module (kernel) interrupt control rtcint f sys mode_select xtal3 xtal4 32 khz
tc1775 data sheet 52 v1.2, 2002-05 preliminary system control unit the system control unit (scu) of the tc1775 handles the system control tasks. all these system functions are tightly coupled, thus, they are conveniently handled by one unit, the scu. the system tasks of the scu are: reset control ? generation of all internal reset signals ? generation of external hdrst reset signal pll control ? pll_clc clock control register power management control ? enabling of several power-down modes ? control of the pll in power-down modes watchdog timer port 5 trace control device identification
tc1775 data sheet 53 v1.2, 2002-05 preliminary interrupt system an interrupt request can be serviced either by the cpu or by the peripheral control processor (pcp). these units are called ?service providers?. interrupt requests are called ?service requests? rather than ?interrupt requests? in this document because they can be serviced by either of the service providers. each peripheral in the tc1775 can generate service requests. additionally, the bus control unit, the debug unit, the pcp, and even the cpu itself can generate service requests to either of the two service providers. as shown in figure 16 , each tc1775 unit that can generate service requests is connected to one or multiple service request nodes (srn). each srn contains a service request control register mod_srcx, where ?mod? is the identifier of the service requesting unit and ?x? an optional index. two buses connect the srns with two interrupt control units, which handle interrupt arbitration among competing interrupt service requests, as follows: the interrupt control unit (icu) arbitrates service requests for the cpu and administers the cpu interrupt arbitration bus. the peripheral interrupt control unit (picu) arbitrates service requests for the pcp and administers the pcp interrupt arbitration bus. units, which can generate service requests are: ? general purpose timer unit (gptu) with 8 srns ? general purpose timer array (gpta) with 54 srns ? two high-speed synchronous serial interfaces (ssc0/ssc1) with 3 srns each ? two asynchronous/synchronous serial interfaces (asc0/asc1) with 4 srns each ? twincan controller with 8 srns ? serial data link module (sdlm) with 2 srns ? two analog/digital converters (adc0/adc1) with 4 srns each ? real time clock (rtc) with 1 srn ? bus control unit (bcu) with 1 srn ? peripheral control processor (pcp) with 4 srns ? central processing unit (cpu) with 4 srns ? debug unit (ocds) with 1 srn the pcp can make service requests directly to itself (via the picu), or it can make service requests to the cpu. the debug unit can generate service requests to the pcp or the cpu. the cpu can make service requests directly to itself (via the icu), or it can make service requests to the pcp. the cpu service request nodes are activated through software. external interrupt inputs in tc1775 are available using the input pins connected to the general-purpose timer unit (gptu). each of the eight gptu i/o pins can be used as an external interrupt input, using the service request nodes of the gptu module. in addition, such an external interrupt input can also trigger a timer function.
tc1775 data sheet 54 v1.2, 2002-05 preliminary figure 16 block diagram of the tc1775 interrupt system note: depending on the selected system frequency f sys , the number of clocks for interrupt arbitration cycles must be selected as follows: f sys 30 mhz: icr.conecyc = 1 f sys > 30 mhz: icr.conecyc = 0 mcb04779 54 srns int. req. 8 srns 8 gptu 54 gpta 3 srns 3 ssc0 3 srns 3 ssc1 4 srns 4 asc0 4 srns 4 asc1 8 srns 8 can 2 srns 2 sdlm 4 srns 4 adc0 4 srns 4 adc1 1 srn 1 rtc 1 srn 1 bcu service request nodes service requestors 8 8 54 2 54 3 3 3 4 4 4 4 8 8 2 2 4 4 4 4 1 1 1 1 pcp interrupt arbitration bus cpu interrupt arbitration bus 2 srns 2 srns interrupt control units 2 pipn pcp int. ack. ccpn 2 interrupt service providers 2 1 1 1 srns 1 debug unit 4 4 4 srns 4 int. req. pipn cpu ccpn int. ack. software interrupt icu picu 3
tc1775 data sheet 55 v1.2, 2002-05 preliminary boot options the tc1775 booting schemes provides a number of different boot options for the start of code execution. table 5 shows the boot options available in the tc1775. table 5 boot selections ocdse brkin cfg [3] cfg [2:0] type of boot boot source initial pc value 11x000 b start from boot rom boot rom bfff fffc h 001 b 010 b 0100 b external memory as slave directly via ebu external memory (cached) a000 0000 h 1100 b external memory as master directly via ebu 0101 b external memory as slave via fpi bus 1101 b external memory as master via fpi bus x011 b 110 b 111 b reserved; don?t use these combinations; 010100 b or 101 b go to halt with ebu enabled as slave ?? 1 go to halt with ebu enabled as master all other combina- tions go to halt with ebu disabled 0 0 don?t care go to external emulator space ? be00 0000 h 1 0 don?t care tri-state chip (deep sleep) ??
tc1775 data sheet 56 v1.2, 2002-05 preliminary power management system the tc1775 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. there are four power management modes: run mode idle mode sleep mode deep sleep mode table 6 describes these features of the power management modes. table 6 power management mode summary mode description run the system is fully operational. all clocks and peripherals are enabled, as determined by software. idle the cpu clock is disabled, waiting for a condition to return it to run mode. idle mode can be entered by software when the processor has no active tasks to perform. all peripherals remain powered and clocked. processor memory is accessible to peripherals. a reset, watchdog timer event, a falling edge on the nmi pin, or any enabled interrupt event will return the system to run mode. sleep the system clock continues to be distributed only to those peripherals programmed to operate in sleep mode. interrupts from operating peripherals, the watchdog timer, a falling edge on the nmi pin, or a reset event will return the system to run mode. entering this state requires an orderly shut-down controlled by the power management state machine. deep sleep the system clock is shut off; only an external signal will restart the system. entering this state requires an orderly shut-down controlled by the power management state machine (pmsm).
tc1775 data sheet 57 v1.2, 2002-05 preliminary on-chip debug support the on-chip debug support of the tc1775 consists of four building blocks: ocds module in the tricore cpu ? on-chip breakpoint hardware ? support of an external break signal ocds module in the pcp ? special debug instruction for program execution tracing trace module of the tricore ? outputs 16 bits per cycle with pipeline status information, pc bus information, and breakpoint qualification information debugger interface (cerberus) ? provided for debug purposes of emulation tool vendors ? accessible through a jtag standard interface with dedicated jtag port pins figure 17 shows a basic block diagram of the building blocks. figure 17 ocds support basic block diagram mcb04810 cerberus & jtag trst tck tms tdi tdo jtag i/o lines tricore cpu ocds pcp scu trace control 16 brkin brkout port 5 trace[15:0] ocdse fpi bus
tc1775 data sheet 58 v1.2, 2002-05 preliminary clock generation unit the clock generation unit (cgu) in the tc1775, shown in figure 18 , consists of an oscillator circuit and a phase-locked loop (pll). the pll can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. the pll also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. it can execute emergency actions if it looses its lock on the external clock. in general, the cgu is controlled through the system control unit (scu) module of the tc1775. figure 18 clock generation unit block diagram besides the two xtal pins for the oscillator, input pins clksel[2:0] and bypass are used for configuration of the clock generation unit. these inputs are checked by the scu which generates the appropriate control signals and latches the state of these signals into register pll_clc. mca04713 oscillator circuit xtal1 xtal2 & f osc phase detect. vco n divider pll f vco 1 0 k divider f sys system_ clk lock detector osc_ok pll locked deep sleep ndiv[2:0] vco_ bypass kdiv[2:0] pll_ bypass clksel[2:0] bypass register pll_clc mux 1 0 mux clock generation unit cgu system control unit scu
tc1775 data sheet 59 v1.2, 2002-05 preliminary pll operation the f vco clock of the pll has a frequency which is a multiple of the externally applied clock f osc . the factor for this is controlled through the value n applied to the divider in the feedback path. n is defined through three pll configuration inputs clksel[2:0]. the k-divider is a software controlled divider. table 8 lists the possible values for k and the resulting division factor. table 7 input frequencies and n factor for f vco clksel[2:0] n-factor f vco = 150 mhz f vco = 160 mhz f vco = 200 mhz 000 b 8 18.75 20 25 001 b 9 16.67 17.76 22.22 010 b 10 15 16 20 011 b 11 13.64 14.55 18.18 100 b 12 12.5 13.33 16.67 101 b 13 11.54 12.31 15.38 110 b 14 10.71 11.43 14.29 111 b 15 10 10.67 13.33 shaded combinations should not be used because the maximum oscillator frequency of 16 mhz is exceeded. table 8 output frequencies f sys derived from various output factors k-factor f sys 1) 1) depending on the selected system frequency f sys , the number of clocks for interrupt arbitration cycles must be selected as follows: f sys 30 mhz: icr.conecyc = 1, f sys > 30 mhz: icr.conecyc = 0. duty cycle [%] selected factor kdiv f vco = 150 mhz f vco = 160 mhz f vco = 200 mhz 2000 b 75 80 100 50 4010 b 37.5 40 50 50 5 2) 2) these odd k-factors should not be used (not tested because of the unsymmetrical duty cycle). 011 b 30 32 40 40 6100 b 24.5 26.67 33.33 50 8101 b 18.75 20 25 50 9 2) 110 b 16.67 17.78 22.22 44 10 111 b 15 16 20 50 16 001 b 9.38 10 12.5 50 shaded combinations cannot not be used because the maximum system clock frequency of 40 mhz is exceeded.
tc1775 data sheet 60 v1.2, 2002-05 preliminary recommended oscillator circuits figure 19 oscillator circuitries for the main oscillator of the tc1775 the following external passive components are recommended: ? crystal: max. 16 mhz ? c 1 , c 2 : 10 pf a block capacitor between v ddosc and v ssosc is recommended, too. for the rtc oscillator of the tc1775 the following external passive components are recommended: ? crystal: 32.768 khz ? c 1 , c 2 : 12 pf note: for crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. mcs04714 tc1775 main oscillator v ddosc v ssosc c 1 1-16 mhz c 2 xtal1 xtal2 tc1775 main oscillator v ddosc v ssosc xtal1 xtal2 external clock signal mcs04716 tc1775 rtc oscillator v dd v ss c 1 32.768 khz c 2 xtal3 xtal4
tc1775 data sheet 61 v1.2, 2002-05 preliminary power supply figure 20 shows the tc1775?s power supply concept, where certain logic modules are individually supplied with power. this concept improves the emi behavior by reduction of the noise cross coupling. also the operation margin is improved in sensitive modules like the a/d converter by noise reduction. figure 20 tc1775 power supply concept tc1775 mcd04878 cpu & control & peripherals pll osc v ddosc (2.5 v) v ddosc v ddpll (2.5 v) v sspll v ddp05 (2.5 v) v ss v ddp813 (3.3 - 5 v) v ss v ddsb (2.5 v) v ss v ddsram (2.5 v) v ss short circuit / broken wire logic short circuit / broken wire logic adc0 control logic adc1 control logic v dda0 (2.5 v) v ssa0 v ddm (5 v) v ssm v ddsc (5 v) v sssc v dda1 (2.5 v) v ssa1 pcp memory dmu pmu gpio ports (p8-p13) ebu ports (p0-p5) v dd (2.5 v) v ss
tc1775 data sheet 62 v1.2, 2002-05 preliminary ports power supply the tc1775?s port power supply concept is shown in figure 21 . the ports assigned with the external bus unit (ebu) are in a separate power supply group for 2.5 v nominal operating voltage. the general purpose input/outputs (gpios) except the ebu provide 3.3 to 5 v input/output acceptance and drive characteristics. figure 21 ports power supply concept power-up sequence during power-up the reset pin porst has to be held active until both power supply voltages have reached at least their minimum values. during the power-up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the difference between v ddp813 and v ddi (i.e. v ddp813 - v ddi ) never drops below -0.3 v ( v ddi = v dd and v ddp05 ). power loss if v ddp813 is dropping below v ddi , external circuitry in the power supply has to ensure, that v ddi is also limited to the same level. if v ddi is dropping below the operating range, v ddp813 may stay active. powering down during powering down (falling of the supply voltages from their regular operating values to zero), it has to be ensured, that the difference between v ddp813 and v ddi ( v ddp813 - v ddi ) never drops below -0.3 v. mca04752 v ss ports 0 to 5 (pads) & schmitt trigger ports 8 to 13 (pads) & schmitt trigger v ddp05 (2.5 v) v ddp813 (3.3 - 5 v) port logic v dd (2.5 v)
tc1775 data sheet 63 v1.2, 2002-05 preliminary identification register values table 9 tc1775 identification registers short name address value pmu_id c7ff ff08 h 0006 c002 h dmu_id d7ff ff08 h 0007 c002 h scu_id f000 0008 h 0003 c002 h manid f000 0070 h 0000 1820 h chipid f000 0074 h 0000 8002 h rtid f000 0078 h 0000 0000 h rtc_id f000 0108 h 0000 5a01 h bcu_id f000 0208 h 0000 6a05 h stm_id f000 0308 h 0000 c002 h jpd_id f000 0408 h 0000 6301 h ebu_id f000 0508 h 0005 c002 h (ba11-step) 0005 c003 h (ba21-step) gptu_id f000 0708 h 0001 c002 h asc0_id f000 0808 h 0000 4401 h asc1_id f000 0908 h 0000 4401 h ssc0_id f000 0a08 h 0000 4503 h ssc1_id f000 0b08 h 0000 4503 h gpta_id f000 1808 h 0002 c001 h adc0_id f000 2208 h 0000 3101 h adc1_id f000 2408 h 0000 3101 h sdlm_id f000 2608 h 0000 4202 h pcp_id f000 3f08 h 000d c001 h can_id f010 0008 h 0000 4110 h cpu_id fffe ff08 h 0000 0202 h
tc1775 data sheet 64 v1.2, 2002-05 preliminary parameter interpretation the parameters listed on the following pages partly represent the characteristics of the tc1775 and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the tc1775 will provide signals with the respective timing characteristics. sr ( s ystem r equirement): the external system must provide signals with the respective timing characteristics to the tc1775. pin classes the tc1775 has three classes of digital i/o pins: ? class a pins, which are 3.3 v to 5 v nominal voltage pins ? class b pins, which are 2.5 v nominal voltage pins (input tolerant for 3.3 v) ? class c pins, which are 2.5 v nominal voltage pins only table 10 shows the assignments of all digital i/o pins to pin classes and to v dd power supply pins. table 10 assignments of digital pins to pin classes and power supply pins pins pin classes power supply port 8 to port 13 clksel[2:0], bypass, cfg[3:0], hdrst class a (nominal 3.0 to 5.25 v) v ddp813 v ss port 0 to 5 trst , tck, tdi, tdo, tms, odcse , brkin , brkout , nmi , porst , clkout, clkin testmode class b (nominal 2.5 v, 3.3 v tolerant) v ddp05 core supply, no pins assigned (nominal 2.5 v) v dd , v ddsram , v ddsb v ddpll v sspll xtal1, xtal2, xtal3, xtal4 class c (nominal 2.5 v) v ddosc v ssosc
tc1775 data sheet 65 v1.2, 2002-05 preliminary absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. parameter symbol limit values unit notes min. max. ambient temperature t a -40 125 c under bias storage temperature t a -65 150 c? junction temperature t j ?150 c under bias voltage on class a power supply pins with respect to v ss v dd -0.5 6.2 v see table 10 voltage on class b and c power supply pins with respect to v ss v dd -0.5 3.25 v ? voltage on power supply pins ?no pins assigned? with respect to v ss v dd -0.5 3.25 v ? voltage on any class a input pin with respect to v ss v in -0.5 v dd + 0.5 v ? voltage on any class b input pin with respect to v ss v in -0.5 3.7 v ? voltage on any class c input pin with respect to v ss v in -0.5 v ddosc + 0.5 v? input current on any pin during overload condition i in -10 10 ma ? absolute sum of all input currents during overload condition i in ? |100| ma ?
tc1775 data sheet 66 v1.2, 2002-05 preliminary package parameters (p-bga-329) operating conditions the following operating conditions must not be exceeded in order to ensure correct operation of the tc1775. all parameters specified in the following table refer to these operating conditions, unless otherwise noticed. parameter symbol limit values unit notes min. max. power dissipation p diss ?1w? thermal resistance r tha ? 23 k/w chip to ambient parameter symbol limit values unit notes min. max. digital supply voltage 1) v ddp813 3.0 5.25 v class a pins v dd 2) 2.3 2.75 v cpu core and class b pins v ddosc 2.3 2.75 v class c pins v ddsb 3) 2.25 2.75 v ? digital ground voltage v ss 0v? ambient temperature under bias t a -40 +125 c? analog supply voltages v dda 2.25 2.75 v ? v ddm 4.5 5.25 v ? analog reference voltage v aref 4 v ddm + 0.05 v 4) analog ground voltage v agnd v ssa - 0.05 v ssa + 0.05 v 5) analog input voltage v ain v agnd v aref v? cpu clock f sys ?40mhz? overload current i ov -10 10 ma 6)7)8) short circuit current i sc -10 10 ma 3)4)9) absolute sum of overload + short circuit currents | i ov |+ | i sc | ?|50|ma 7) external load capacitance c l ?50pf?
tc1775 data sheet 67 v1.2, 2002-05 preliminary 1) digital supply voltages applied to the tc1775 must be static regulated voltages which allow a typical voltage swing of 10%. 2) this v dd specification is applicable for the power supply pins: v dd , v ddosc , v ddpll , v ddsram , v ddp05 , and v ddsb . in order to minimize the danger of latch-up conditions, these 2.5 v v dd power supply pins should be kept at the same voltage level during normal operating mode. this condition is typically achieved by generating the 2.5 v power supplies from a single voltage source. the condition is also valid in normal operating mode if a separate stand-by power supply v ddsb is used. 3) the minimum voltage at pin v ddsb during tc1775 power down mode is 1.8 v in order to keep the contents of sbram valid. the core power supply v dd must be below the standby power supply v dd < v ddsb + 0.3 v. 4) the value of v aref is permitted to be within the range of v ssa -0.05v< v aref < v ddm + 0.05 v. the value specified for the total unadjusted error (tue) is not guaranteed while the v aref is out of the specified range. 5) the value of v agnd is permitted to be within the range of v ssa -0.05v< v agnd < v ddm + 0.05 v. the value specified for the total unadjusted error (tue) is not guaranteed while the v agnd is out of the specified range. 6) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v dd + 0.5 v or v ov < v ss - 0.5 v). the absolute sum of input overload currents on all port pins may not exceed 50 ma . the supply voltage must remain within the specified limits. 7) not 100% tested, guaranteed by design and characterization. 8) applicable for analog inputs. 9) applicable for digital inputs.
tc1775 data sheet 68 v1.2, 2002-05 preliminary dc characteristics input/output dc-characteristics v ss = 0 v; t a = -40 c to +125 c; parameter 1) symbol limit values unit test conditions min. max. class a pins ( v ddp813 = 3.0 to 5.25 v) output low voltage 2) v ol cc ? 0.45 v i ol =2.4ma 3) i ol =600 a 4) v ddp813 = 4.5 to 5.25 v 0.2 v ddp813 v i ol =2.4ma i ol =600 a 4) v ddp813 = 3.0 to 4.49 v output high voltage 2) v oh cc 0.7 v ddp813 ?v i oh =-2.4ma i oh =-600 a 4) v ddp813 = 4.5 to 5.25 v v i oh =-2.4ma i oh =-600 a 4) v ddp813 = 3.0 to 4.49 v input low voltage 5) v il sr -0.5 0.8 v v ddp813 = 4.5 to 5.25 v (ttl) 0.43 v ddp813 v v ddp813 = 4.5 to 5.25 v (cmos) 0.2 v ddp813 v v ddp813 = 3.0 to 4.49 v (cmos) input high voltage 5) v ih sr 2.0 v ddp813 +0.5 v v ddp813 = 4.5 to 5.25 v (ttl) 0.73 v ddp813 v v ddp813 = 3.0 to 5.25 v (cmos) pull-up current 6) i puh cc ? 10 a v out = v ddp813 -0.02 v i pul cc -120 ? a v out = 0.5 v ddp813 pull-down current 7) i pdl cc 10 ? a v out = 0.02 v i pdh cc ? 120 a v out = 0.5 v ddp813
tc1775 data sheet 69 v1.2, 2002-05 preliminary class b pins ( v ddp05 = 2.30 to 2.75 v) output low voltage v ol cc ? 0.2 v ddp05 v i ol =2.4ma 0.45 i ol =600 a output high voltage v oh cc 0.7 v ddp05 ?v i oh =-2.4ma 0.9 v ddp05 ?v i oh =-600 a input high voltage v ih sr 0.7 v ddp05 3.7 v ? input low voltage v il sr -0.5 0.2 v ddp05 v? pull-up current 6) i puh cc ? 10 a v out = v ddp05 - 0.02 v i pul cc -60 ? a v out = 0.5 v ddp05 pull-down current 7) i pdl cc 10 ? a v out = 0.02 v i pdh cc ? 60 a v out = 0.5 v ddp05 class a and b pins input hysteresis hys cc 0.065 v ddpx 8) ? v ttl and cmos 9) input leakage current (digital i/o) i oz2 cc ? 500 na 0 v < v in < v ddpx 8) peak short-circuit current peak back-drive current (per digital pin) peak time & period time 10)11) i scbdpeak sr ? 20 ma 12)9) input/output dc-characteristics (cont?d) v ss = 0 v; t a = -40 c to +125 c; parameter 1) symbol limit values unit test conditions min. max.
tc1775 data sheet 70 v1.2, 2002-05 preliminary constant short-circuit current constant back-drive current (per digital pin) i scbdcons sr ? 10 ma 12)9) pin capacitance 9) (digital i/o) c io cc ? 10 pf f = 1 mhz t a = 25 c class c pins ( v ddosc = 2.30 to 2.75 v), see page 76 1) all class a pins of the tc1775 are equipped with low-noise output drivers, which significantly improve the device?s emi performance. these low-noise drivers deliver their maximum current only until the respective target output level is reached. after that the output current is reduced. this results in an increased impedance of the driver, which attenuates electrical noise from the connected pcb tracks. the current, which is specified in column ?test conditions?, is delivered in any case. 2) this specification is not valid for outputs of gpio lines, which are switched to open drain mode. in open drain mode the output will float and the voltage results from the external circuitry. 3) output drivers in high current mode. 4) condition for output driver in dynamic current mode & low current mode ? guaranteed by design characterization. 5) input characteristics can be switched between ttl and cmos via register px_picon except for dedicated pins which have cmos input characteristics. 6) the maximum current can be drawn while the respective signal line remains inactive. 7) the minimum current must be drawn in order to drive the respective signal line active. 8) in case of class b pins v ddx = v ddp05 . in case of class a pins v ddx = v ddp813 . 9) guaranteed by design characterization. 10) the max. peak-short-circuit current resp. max. peak-back-drive current is limited by max. 20 ma and the peak period equivalent of 10 ma constant-short-circuit current resp. 10 ma constant-back-drive current. the integral of i scbdpeak over the peak period is thus limited to 10 ma (provided: i scbdpeak 20 ma). 11) to be defined for class b pads. 12) short-circuit or back-drive conditions during operation occur if the voltage on the respective pin exceeds the specified operating range (i.e. v scbd > v ddpx +0.5v or v scbd < v ss -0.5v ) or a short circuit condition occurs on the respective pin. the absolute sum of input i scbd and i ov currents on all port pins must not exceed 100 ma at any time. the supply voltage ( v ddpx and v ss ) must remain within the specified limits. under short- circuit conditions the corresponding pin is not ready for use. in case of class b pins v ddx = v ddp05 . in case of class a pins v ddx = v ddp813 . input/output dc-characteristics (cont?d) v ss = 0 v; t a = -40 c to +125 c; parameter 1) symbol limit values unit test conditions min. max.
tc1775 data sheet 71 v1.2, 2002-05 preliminary pull-up/pull-down characteristics figure 22 pull-up/pull-down characteristics of class a pins mcd05235 0 0 a i v v 12 34 56 pull-up 0 0 a i v v 12 34 56 pull-down best case nominal 100 200 300 400 500 600 700 100 200 300 400 500 600 700 worst case nominal best case worst case
tc1775 data sheet 72 v1.2, 2002-05 preliminary figure 23 pull-up/pull-down characteristics of class b pins note: the pull-up/pull-down characteristics as shown in figure 22 and figure 23 are guaranteed by design characterization. mcd05236 0 0 50 100 150 200 250 a i v v 0.5 1 1.5 2 2.5 3 pull-up 0 0 50 100 150 200 250 a i v v 0.5 1 1.5 2 2.5 3 pull-down best case nominal worst case worst case nominal best case
tc1775 data sheet 73 v1.2, 2002-05 preliminary ad converter characteristics t a = -40 c to +125 c; v ss =0v; parameter symbol limit values unit test conditions min. typ. max. analog supply voltages v ddax sr 2.25 2.5 2.75 v 1) v ddm sr 4.5 5 5.25 v ? v ddsc sr v ddm - 0.05 ? v ddm + 0.05 v? analog ground voltage v ssax sr -0.1 ? 0.1 v 2) analog reference voltage v arefx sr 4? v ddm + 0.05 v 3) analog reference ground v agndx sr v ssax - 0.05 ? v ssax + 0.05 v 4) analog input voltage range v ain sr v agndx ? v arefx v? internal adc clock f ana 0.5 ? 2 mhz ? power-up calibration time t puc ? ? 3328 (3 + con.cps) t bc s? sample time t s cc (3 + con.cps) (chconn.stc + 2) t bc s 5) 6 t bc ?? s conversion time t c cc t s + (30 + con.cps 4) t bc + 2 t div s for 8-bit conv. 5) t s + (36 + con.cps 4) t bc + 2 t div s for 10-bit conv. 5) t s + (42 + con.cps 4) t bc + 2 t div s for 12-bit conv. 5) total unadjusted error tue 6) cc ? ? 1 lsb for 8-bit conv. ?? 2 lsb for 10-bit conv. ?? 6 lsb for 12-bit conv. overload current 7) i aov1 cc 8) -2 ? +5 ma ? -2 0 ma k a =1.0 10 -3 0+5ma k a =1.0 10 -4 i aov2 cc 9) -4 ? +10 ma ? -4 0 ma k a =1.0 10 -3 0+10ma k a =1.0 10 -4
tc1775 data sheet 74 v1.2, 2002-05 preliminary overload coupling factor 10) k a cc ? ? 1.0 10 -3 ?see i aov1 and i aov2 1.0 10 -4 ? input leakage current at analog inputs i oz1 cc ? ? 200 na 0 v < v in < v dda 1) input leakage current at v agnd and v aref i oz2 cc ? ? 500 na 0 v < v in < v dda 1) switched cap. at the positive reference voltage input c arefsw cc ?1520 pf 11) switched cap. at the negative reference voltage input c agnds cc ?1520 pf 11) total cap. at the analog voltage input c aintot cc ?1215 pf? switched cap. at the analog voltage input c ainsw cc ? ? 10 pf 12) on resistance of the transmission gates in the analog voltage path r ain cc ? ? 0.7 k ? ? 1) v ddax = v dda0 for a/d converter adc0 and v ddax = v dda1 for a/d converter adc1. 2) v ssax = v ssa0 for a/d converter adc0 and v ssax = v ssa1 for a/d converter adc1. 3) the value of v aref is permitted to be within the range of v ssa - 0.05 v < v aref < v ddm + 0.05 v. the value specified for the total unadjusted error (tue) is not guaranteed while the v aref is out of the specified range. 4) the value of v agnd is permitted to be within the range of v ssa - 0.05 v < v agnd < v ddm + 0.05 v. the value specified for the total unadjusted error (tue) is not guaranteed while the v agnd is out of the specified range. 5) definitions for cps, stc, t bc and t div see figure 25 . 6) tue is tested at v aref =5v, v agnd = 0 v and v ddm =4.9v. 7) analog overload conditions during operation occur if the voltage on the respective adc pin exceeds the specified operating range (i.e. v aov > v ddm + 0.5 v or v aov < v ssm - 0.5 v ) or a short circuit condition occurs on the respective adc pin. the absolute sum of input currents on all port pins must not exceed 10 ma at any time. the supply voltage ( v dd , v dda0 , v dda1 and v ss , v ssa0 , v ssa1 ) must remain within the specified limits. under short-circuit conditions the corresponding pin is not ready for use. 8) applies for one analog input pin. 9) applies for two adjacent analog input pins. ad converter characteristics (cont?d) t a = -40 c to +125 c; v ss =0v; parameter symbol limit values unit test conditions min. typ. max.
tc1775 data sheet 75 v1.2, 2002-05 preliminary figure 24 equivalent circuitry of analog input note: this equivalent circuitry for an analog input is also valid for the reference inputs v aref and v agnd . 10) the overload coupling factor ( k a ) defines the worst case relation of an overload condition ( i ov ) at one pin to the resulting leakage current ( i leak ) into an adjacent pin: | i leak | = k a | i ov |. thus under overload conditions an additional error leakage voltage ( u ael ) will be induced onto an adjacent analog input pin due to the resistance of the analog input source ( r ain ). that means u ael = r ain | i leak |. see also section 7.1.6 ?error through overload conditions? in the tc1775 peripheral units user?s manual for further explanations. 11) this represents an equivalent switched capacitance. this capacitance is not switched to the reference voltage at once. instead of this smaller capacitances are successively switched to the reference voltage. alternatively, the redistributed charge could be specified. 12) the switched capacitance at the analog voltage input must be charged within the sampling time. alternatively, the redistributed charge could be specified. mcs04879 r ain, source = v ain c ain, block r ain, on c aintot - c ainsw c ainsw a/d converter
tc1775 data sheet 76 v1.2, 2002-05 preliminary figure 25 adc clock circuit note: the frequency of f adc is the system clock frequency ( f sys ) divided by the value of bit field adcx_clc.rmc. oscillator pins (class c pins) t a = -40 c to +125 c; v ddosc = 2.30 to 2.75 v; v ssosc = 0 v; parameter symbol limit values unit test conditions min. max. input low voltage at xtal1, xtal3 v ilx sr -0.5 0.3 v ddosc v? input high voltage at xtal1, xtal3 v ihx sr 0.7 v ddosc v ddosc +0.5 v? input current at xtal1 i ix1 cc ? 20 a0v < v in < v ddosc input current at xtal3 i ix3 cc ? 0.5 a0v < v in < v ddosc input leakage current xtal1, xtal3 1) 1) only applicable in deep sleep mode. i oz cc ? 200 na 0 v< v in < v ddosc mca04657 programmable clock divider (1:1) to (1:128) 4:1 3:1 f bc f div peripheral clock divider (1:1) to (1:8) f adc f ana programmable counter sample time t s con.pcd con.ctc con.cps chconn.stc f timer control/status logic interrupt logic external trigger logic external multiplexer logic request generation logic a/d converter module arbiter (1:20) control unit (timer)
tc1775 data sheet 77 v1.2, 2002-05 preliminary power supply current t a = -40 c to +125 c; parameter symbol limit values unit test conditions min. typ. 1) 1) parameters in this column are tested at 25 c, 40 mhz system clock (if applicable) and nominal v dd voltages. max. active mode supply current i dd cc ? ? 250 ma porst = v il 2)3) 2) these parameters are tested at v ddmax and 40 mhz system clock with all outputs disconnected and all inputs at v il or v ih . 3) these power supply currents are defined as the sum of all currents at the v dd power supply lines: v dd + v ddp05 + v ddp 813 + v ddsram + v ddsb + v ddpll + v ddosc + v ddsc + v ddm + v dda0 + v dda1 ? 266 320 ma sum of i dds 4) 4) these power consumption characteristics are measured while running a typical application pattern. the power consumption of modules can increase or decrease using other application programs. the pll is inactive during this measurement. ?36? ma i dd at v ddp05 4) ?4 ? ma i dd at v ddp813 4) ? 219 ? ma i dd at v dd and v ddsram 4) ?3 4) 80 5) 5) this parameter has been evaluated at design characterization using an untypical test pattern that makes extensive usage of the sbsram. ma i dd at v ddsb ?4 ? ma i dd at v ddsc and v ddax 4) idle mode supply current i id cc ? 80 200 ma porst = v ih 1)2)6)7) 6) all peripherals are enabled and in idle state. 7) guaranteed by design characterization. sleep mode supply current i sl cc ? 50 160 ma porst = v ih 1)2)7) deep sleep mode supply current i ds cc ? 4 1000 aporst = v ih 8) 8) i ds is the sum of all power supply currents except v ddsb . stand-by pin power supply current i sb cc ? 1 200 a i dd at v ddsb 9) 9) tc1775 in deep sleep mode. ? 1 120 a 10) 10) all other v dd pins are at 0v; t j =150 c; v ddsb =2.0v.
tc1775 data sheet 78 v1.2, 2002-05 preliminary ac characteristics output rise/fall times class a drivers (gpio/peripheral ports 8 to 13): v ddp813 = 4.5 to 5.25 v; v ss = 0 v class b drivers (bus interface ports 0 to 5): v ddp05 = 2.30 to 2.75 v; v ss = 0 v t a = -40 c to +125 c, unless otherwise noted; f sys = 40 mhz parameter symbol limit values unit test conditions min. typ. max. class a pins nominal output rise/ fall time 1) 1) measured from 10% output level to 90% output level and vice versa. t rfanom cc ?5?ns t a = 25 c, c l = 50 pf, v ddp813 = 5.0 v px_pocon.pec = 00 b px_pocon.pdc = 0x b maximal output rise/ fall time 1) t rfamax cc ??12ns c l =50pf px_pocon.pec = 00 b px_pocon.pdc = 0x b slow output rise/fall time 1) t rfaslow cc ??55ns c l = 100 pf px_pocon.pec = 01 b px_pocon.pdc = 0x b class b pins output rise/fall time 1) t rfbmax cc ??4nsfor clkout c l = 50 pf ? ? 7 ns for all class b pins except clkout c l = 50 pf
tc1775 data sheet 79 v1.2, 2002-05 preliminary testing waveforms t a = -40 c to +125 c; frequency: max. 40 mhz; class a pins: v ddp813 = 3.0 to 5.25 v; v ss = 0 v; figure 26 testing waveforms for class a pins class b and class c pins: v dd = 2.30 to 2.75 v; v ss =0v; v ddosc = 2.30 to 2.75 v; v ssosc =0v; figure 27 testing waveforms for class b and class c pins figure 28 tri-state testing waveforms for class b pins mct04880 v ihmin v ilmax v ohmin v olmax v ohmin v olmax test points ac inputs during testing are driven with v ihmin for a logic 1 and v ilmax for a logic 0. timing measurements are made at v ohmin for a logic 1 and v olmax for a logic 0. input and output low/high max./min. voltages are defined at page 68 . mct04881 v ihmin v ilmax v dd / 2 test points v dd / 2 ac inputs during testing are driven with v ihmin for a logic 1 and v ilmax for a logic 0. timing measurements are made at v dd /2 for a logic 1 and for a logic 0. input low/high max./min. voltages are defined at page 69 and page 76 . mct05074 v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded v oh / v ol level occurs ( i oh / i ol = 15 ma).
tc1775 data sheet 80 v1.2, 2002-05 preliminary input clock timing v ddosc = 2.30 to 2.75 v; v ssosc = 0 v; t a = -40 c to +125 c; figure 29 input clock timing parameter symbol limit values unit min. max. oscillator clock frequency direct drive f osc sr (= 1/ t osc ) 116mhz with pll 10 16 mhz input clock frequency driving at xtal1 direct drive 1/ t oscdd sr ?40mhz with pll 10 30 mhz input clock high time t 1 sr 7 ? ns input clock low time t 2 sr 7 ? ns input clock rise time t 3 sr ? 4 ns input clock fall time t 4 sr ? 4 ns mct04882 0.5 v ddosc input clock at xtal1 t osc t 1 t 2 v ihx v ilx t 4 t 3
tc1775 data sheet 81 v1.2, 2002-05 preliminary clkout timing v ss =0v; v ddp05 = 2.30 to 2.75 v; t a =-40 c to +125 c; c l = 50 pf; figure 30 clkout output clock timing parameter symbol limit values unit min. typ. max. clock period t clkout cc 25??ns clock high time t 5 cc7.5??ns clock low time t 6 cc7.5??ns clock rise time t 7 cc??4ns clock fall time t 8 cc??4ns clock duty cycle t 5 /( t 5 + t 6 ) dc cc 45 50 55 % 0.9 v ddp mct04883 0.5 v ddp05 clkout t clkout t 5 t 6 0.1 v ddp t 8 t 7
tc1775 data sheet 82 v1.2, 2002-05 preliminary pll parameters note: all pll characteristics defined on this and the next page are guaranteed by design characterization. v ss =0v; v dd = 2.30 to 2.75 v; t a =-40 c to +125 c; phase locked loop operation when pll operation is enabled and configured (see figure 18 and page 59 ), the pll clock f vco (and with it the system clock f sys ) is constantly adjusted to the selected frequency. the relation between f vco and f sys is defined by: f vco =k f sys . the pll causes a jitter of f sys and also of clkout, which is directly derived from f sys and which has its frequency. the following two formulas define the (absolute) approximate maximum value of jitter d n in ns dependent on the k-factor, the system clock frequency f sys in mhz, and the number p of consecutive f sys periods. [1] [2] with rising number p of clock cycles the maximum jitter increases linearly up to a value of p that is defined by the k-factor of the pll. beyond this value of p the maximum accumulated jitter remains at a constant value. further, a lower system clock frequency f sys results in a higher maximum jitter. figure 31 gives an example for the jitter curves with k =8. parameter symbol limit values unit min. max. accumulated jitter d n see figure 31 ? vco frequency range f vco 150 200 mhz pll base frequency f pllbase 40 130 mhz pll lock-in time t l ?200 s for p < 23.5 k d n [ns] = 3.9 f sys [mhz] p + 1.2 for p > 23.5 k d n [ns] = 91.7 f sys [mhz] k + 1.2
tc1775 data sheet 83 v1.2, 2002-05 preliminary figure 31 approximated maximum accumulated pll jitter (for k = 8) note: for safe clock generation and pll operation the definitions and restrictions as defined at pages 58 , 59 , and 80 must be regarded. mcd05237 0 1.0 p ns d n 1.2 1.4 1.6 2.0 12 34 56 d n p k k = 8 20 mhz 25 mhz 33 mhz 40 mhz = max. jitter = number of consecutive f sys periods = k-divider of pll
tc1775 data sheet 84 v1.2, 2002-05 preliminary ebu demultiplexed timing v ss =0v; v ddp05 = 2.30 to 2.75 v; t a =-40 c to +125 c; c l = 50 pf; parameter symbol limit values unit min. max. output delay from clkout t 10 cc 0 9 ns output delay from clkout t 11 cc -2 4 ns data setup to clkout t 12 sr 9 ? ns data hold from clkout 1) 1) valid for ebu_busconx.26 = 0. t 13 sr 1 ? ns data valid after clkout 1) t 15 cc 2 ? ns data setup to clkin 2) 2) valid for ebu_busconx.26 = 1 (early sample feature). not applicable for tc1775 ba11 step. t 31 sr see page 90 ?ns data hold from clkin 2) t 32 sr see page 90 ?ns
tc1775 data sheet 85 v1.2, 2002-05 preliminary figure 32 ebu demultiplexed read timing note: wait timing see figure 36 . address valid data valid mct05075 clkin adv rd rd/wr d[31:0] normal sampling bc[3:0] t 10 t 11 t 11 t 10 t 12 t 13 t 11 t 10 t 11 t 10 t 11 t 11 t 10 a[25:0] svm code csx data valid t 31 t 32 d[31:0] early sampling clkout 1) 1) early sampling for d[31:0] not available in tc1775 ba11 step.
tc1775 data sheet 86 v1.2, 2002-05 preliminary figure 33 ebu demultiplexed write timing data valid mct04885 clkout adv csx rd rd/wr d[31:0] bc[3:0] t 10 t 11 t 11 t 10 t 11 t 10 t 11 t 10 t 11 t 11 t 10 t 15 t 10 address valid 1) code remains at high level during a demultiplexed write cycle a[25:0] code 1) svm
tc1775 data sheet 87 v1.2, 2002-05 preliminary ebu multiplexed timing v ss =0v, v ddp05 = 2.30 to 2.75 v; t a =-40 c to +125 c; c l = 50 pf; figure 34 ebu multiplexed read timing parameter symbol limit values unit min. max. output delay from clkout 1) 1) the following condition is always valid: t 25 < t 20 t 20 cc -2 10 ns output delay from clkout t 21 cc -2 4 ns data setup to clkout t 22 sr 9 ? ns data hold from clkout t 23 sr 1 ? ns address and data valid after clkout 1) t 25 cc 2 ? ns address valid mct04886 clkout data in ad[31:0] ale rd rd/wr bc[3:0] t 20 t 25 t 22 t 23 t 20 t 20 t 20 t 21 t 21 t 20 t 21 t 21 t 20 code svm t 20 t 20 csx
tc1775 data sheet 88 v1.2, 2002-05 preliminary figure 35 ebu multiplexed write timing address valid mct04887 clkout data out ad[31:0] ale csx rd rd/wr bc[3:0] t 20 t 25 t 20 t 20 t 20 t 20 t 21 t 21 t 20 t 21 t 21 t 20 t 20 t 25 t 20 code 1) svm 1) code remains at high level during a multiplexed write cycle
tc1775 data sheet 89 v1.2, 2002-05 preliminary wait timing (fpi bus to external memory) v ss =0v; v ddp05 = 2.30 to 2.75 v; t a =-40 c to +125 c; c l = 50 pf; figure 36 wait timing (from fpi bus to external memory) parameter symbol limit values unit min. max. wait setup to clkout t 50 sr 14 1) 1) guaranteed by design characterization. ?ns wait hold from clkout t 51 sr 14 1) ?ns wait setup to clkout t 52 sr 7 ? ns wait hold from clkout t 53 sr 2 ? ns mct04888 clkout t 50 t 51 t 50 t 51 wait synchronous mode clkout t 52 t 53 t 52 t 53 wait asynchronous mode
tc1775 data sheet 90 v1.2, 2002-05 preliminary ebu burst mode timing v ss =0v, v ddp05 = 2.30 to 2.75 v; t a =-40 c to +125 c; c l = 50 pf; figure 37 burst mode timing (instruction read) note: burst mode and external flash related application hints are described in a separate application note. parameter symbol limit values unit min. max. output delay from clkin t 30 cc 0 14 ns data setup to clkin t 31 sr 2 1) 1) guaranteed by design characterization. ?ns data hold from clkin t 32 sr 3 1) ?ns address valid valid v alid mct04889 clkin t 30 t 30 t 30 t 30 t 30 t 30 t 30 t 32 t 31 t 32 t 31 a[25:2] cs0 code rd baa adv d[15:0] note: wait must be 1 during a burst mode read cycle. t 30 t 30
tc1775 data sheet 91 v1.2, 2002-05 preliminary ebu arbitration signal timing v ss =0v, v ddp05 = 2.30 to 2.75 v; t a =-40 c to +125 c; c l = 50 pf; figure 38 ebu arbitration signal timing parameter symbol limit values unit min. max. output delay from clkout t 40 cc ? 3 ns data setup to clkout t 41 sr 8 ? ns data hold from clkout t 42 sr 2 ? ns mct04890 clkout hlda output breq output t 40 t 40 t 40 t 40 clkout t 42 hold input t 41 t 42 t 41 hlda input
tc1775 data sheet 92 v1.2, 2002-05 preliminary ebu external access timing v ss =0v, v ddp05 = 2.30 to 2.75 v; t a =-40 c to +125 c; c l = 50 pf; parameter symbol limit values unit min. max. csfpi , bc[3:0] , a[23:2] setup before rd or rd/wr t 43 sr 3 ? ns data valid after rd t 44 cc 2 t clkout ?ns wait active after rd or rd/wr t 45 cc ? 11 ns rd/wait float after rd or rd/wr t 46 cc ? 20 ns data setup to rd/wr t 47 sr 3 ? ns data hold from rd/wr t 48 sr 3 ? ns
tc1775 data sheet 93 v1.2, 2002-05 preliminary figure 39 ebu external access timing (external master to fpi bus) data valid data valid mct04891 t 43 t 44 t 46 t 45 a[23:2] bc[3:0] csfpi rd rd/wr ad[31:0] wait read timing valid address & byte control t 43 t 45 a[23:2] bc[3:0] csfpi rd rd/wr ad[31:0] wait write timing valid address & byte control valid address & byte control t 48 t 47 t 46 t 46
tc1775 data sheet 94 v1.2, 2002-05 preliminary port 5 (trace port) timing this timing is applicable for port 5 when cpu or pcp trace mode is enabled (scu_con.eten = 1). v ss =0v; v ddp05 = 2.30 to 2.75 v; t a =-40 c to +125 c; c l = 50 pf; figure 40 port 5 timing parameter symbol limit values unit min. max. port 5 lines high/low from clkout t 55 cc -4 5 ns mct04892 clkout t 55 p5[15:0] old state new state
tc1775 data sheet 95 v1.2, 2002-05 preliminary ssc master mode timing v ss =0v; v ddp813 = 4.5 to 5.25 v; t a = -40 c to +125 c; c l = 50 pf; figure 41 ssc master mode timing parameter symbol limit values unit min. max. sclk/mtsr low/high from clkout 1) 1) this parameter is valid for high current mode output driver characteristic and normal timing edge characteristic (p13_pocon.pecx = 00 b and p13_pocon.pdcx = 00 b ). t 60 cc ? 7 ns mrst setup to slck rising/falling edge t 61 sr 14 2) 2) guaranteed by design characterization. ?ns mrst hold from slck rising/falling edge t 62 sr 14 2) ?ns state n mct04893 clkout sclk t 60 mtsr t 60 t 61 t 62 data valid state n-1 state n+1 t clkout t 60 mrst note: the timing diagram assumes the highest possible baud rate operation. ( f ssc = f clkout , sscx_clc.rmc = 1, sscx_br.br_value = 0000 h )
tc1775 data sheet 96 v1.2, 2002-05 preliminary package outlines 0.35 4 x 1.27 = 5.08 ? 0.15 329x 22 x 1.27 = 27.94 1.95 x 45? 4x 26 31 ?.2 ? 0.6 (0.56) 1.17 ?.05 ?.1 +0.14 -0.16 ?.76 30? ?.3 22 x 1.27 = 27.94 4 x 1.27 = 5.08 a23 1.27 2.52 max. index marking b a 26 31 ? ?.2 b m m c a c c 0.2 c ac1 a1 p-bga-329 (plastic ball grid array package) gpa09280 you can find all of our packages, sorts of packing and others in our infineon internet page ?roducts? http://www.infineon.com/products. dimensions in mm smd = surface mounted device
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